公开(公告)号：US10310865B2

公开(公告)日：2019-06-04

申请号：US15100267

申请日：2013-12-27

Applicant: Intel Corporation

Inventor： Jiewen Yao ,  Vincent Zimmer ,  Nicholas Adams ,  Willard Wiseman ,  Giri Mudusuru ,  Nuo Zhang

IPC: G06F9/00 ,  G06F15/177 ,  G06F9/4401 ,  G06F9/445 ,  G06F21/57

Abstract: The present disclosure is directed to controlled customization of silicon initialization. A device may comprise, for example, a boot module including a memory on which boot code is stored, the boot code including at least an initial boot block (IBB) module that is not customizable and a global platform database (GPD) module including customizable data. The IBB module may include a pointer indicating GPD module location. The customizable data may comprise configurable parameters and simple configuration language (SCL) to cause the device to execute at least one logical operation during execution of the boot code. The GPD module may further comprise a pointer indicating SCL location. The boot code may be executed upon activation of the device, which may cause the IBB module to load an interpreter for executing the SCL. The interpreter may also verify access request operations in the SCL are valid before executing the access request operations.

公开(公告)号：US10592253B2

公开(公告)日：2020-03-17

申请号：US15426722

申请日：2017-02-07

Applicant: Intel Corporation

Inventor： Giri P. Mudusuru ,  Rangasai V. Chaganty ,  Chasel Chiu ,  Satya P. Yarlagadda ,  Nivedita Aggarwal ,  Nuo Zhang

IPC: G06F9/4401 ,  G06F3/06

Abstract: Technologies for pre-memory phase initialization include a computing device having a processor with a cache memory. The computing device may determine whether a temporary memory different from the cache memory of the processor is present for temporary memory access prior to initialization of a main memory of the computing device. In response to determining that temporary memory is present, a portion of the basic input/output instructions may be copied from a non-volatile memory of the computing device to the temporary memory for execution prior to initialization of the main memory. The computing device may also initialize a portion of the cache memory of the processor as Cache as RAM for temporary memory access prior to initialization of the main memory in response to determining that temporary memory is not present. After initialization, the main memory may be configured for subsequent memory access. Other embodiments are described and claimed.

公开(公告)号：US20170147357A1

公开(公告)日：2017-05-25

申请号：US15426722

申请日：2017-02-07

Applicant: Intel Corporation

Inventor： Giri P. Mudusuru ,  Rangasai V. Chaganty ,  Chasel Chiu ,  Satya P. Yarlagadda ,  Nivedita Aggarwal ,  Nuo Zhang

IPC: G06F9/44 ,  G06F3/06

CPC classification number: G06F9/4401 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0679 ,  G06F9/4403

Abstract: Technologies for pre-memory phase initialization include a computing device having a processor with a cache memory. The computing device may determine whether a temporary memory different from the cache memory of the processor is present for temporary memory access prior to initialization of a main memory of the computing device. In response to determining that temporary memory is present, a portion of the basic input/output instructions may be copied from a non-volatile memory of the computing device to the temporary memory for execution prior to initialization of the main memory. The computing device may also initialize a portion of the cache memory of the processor as Cache as RAM for temporary memory access prior to initialization of the main memory in response to determining that temporary memory is not present. After initialization, the main memory may be configured for subsequent memory access. Other embodiments are described and claimed.

公开(公告)号：US09563437B2

公开(公告)日：2017-02-07

申请号：US14318129

申请日：2014-06-27

Applicant: Intel Corporation

Inventor： Giri P. Mudusuru ,  Rangasai V. Chaganty ,  Chasel Chiu ,  Satya P. Yarlagadda ,  Nivedita Aggarwal ,  Nuo Zhang

IPC: G06F9/00 ,  G06F15/177 ,  G06F9/44

CPC classification number: G06F9/4401 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0679 ,  G06F9/4403

Abstract: Technologies for pre-memory phase initialization include a computing device having a processor with a cache memory. The computing device may determine whether a temporary memory different from the cache memory of the processor is present for temporary memory access prior to initialization of a main memory of the computing device. In response to determining that temporary memory is present, a portion of the basic input/output instructions may be copied from a non-volatile memory of the computing device to the temporary memory for execution prior to initialization of the main memory. The computing device may also initialize a portion of the cache memory of the processor as Cache as RAM for temporary memory access prior to initialization of the main memory in response to determining that temporary memory is not present. After initialization, the main memory may be configured for subsequent memory access. Other embodiments are described and claimed.

Abstract translation: 用于预存储器相位初始化的技术包括具有具有高速缓存存储器的处理器的计算设备。 在初始化计算设备的主存储器之前，计算设备可以确定是否存在与处理器的高速缓冲存储器不同的临时存储器用于临时存储器访问。 响应于确定存在临时存储器，可以在初始化主存储器之前将基本输入/输出指令的一部分从计算设备的非易失性存储器复制到临时存储器以供执行。 响应于确定临时存储器不存在，计算设备还可以在处理器的初始化之前将处理器的高速缓冲存储器的一部分初始化为高速缓冲存储器作为用于临时存储器访问的RAM。 初始化之后，可以将主存储器配置为用于后续存储器访问。 描述和要求保护其他实施例。

公开(公告)号：US11068276B2

公开(公告)日：2021-07-20

申请号：US16431444

申请日：2019-06-04

Applicant: Intel Corporation

Inventor： Jiewen Yao ,  Vincent Zimmer ,  Nicholas Adams ,  Willard Wiseman ,  Giri Mudusuru ,  Nuo Zhang

IPC: G06F9/00 ,  G06F15/177 ,  G06F9/4401 ,  G06F9/445 ,  G06F21/57

Abstract: The present disclosure is directed to controlled customization of silicon initialization. A device may comprise, for example, a boot module including a memory on which boot code is stored, the boot code including at least an initial boot block (IBB) module that is not customizable and a global platform database (GPD) module including customizable data. The IBB module may include a pointer indicating GPD module location. The customizable data may comprise configurable parameters and simple configuration language (SCL) to cause the device to execute at least one logical operation during execution of the boot code. The GPD module may further comprise a pointer indicating SCL location. The boot code may be executed upon activation of the device, which may cause the IBB module to load an interpreter for executing the SCL. The interpreter may also verify access request operations in the SCL are valid before executing the access request operations.