公开(公告)号：US20160299847A1

公开(公告)日：2016-10-13

申请号：US15190231

申请日：2016-06-23

Applicant: Intel Corporation

Inventor： Zeshan A. Chishti ,  Christopher B. Wilkerson ,  Seth Pugsley ,  Peng-Fei Chuang ,  Robert L. Scott ,  Aamer Jaleel ,  Shih-Lien L. Lu ,  Kingsum Chow

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F9/3802 ,  G06F9/3808 ,  G06F9/383 ,  G06F2212/6026

Abstract: A processor includes a cache, a prefetcher module to select information according to a prefetcher algorithm, and a prefetcher algorithm selection module. The prefetcher algorithm selection module includes logic to select a candidate prefetcher algorithm determine and store memory addresses of predicted memory accesses of the candidate prefetcher algorithm when performed by the prefetcher module, determine cache lines accessed during memory operations, and evaluate whether the determined cache lines match the stored memory addresses. The prefetcher algorithm selection module further includes logic to adjust an accuracy ratio of the candidate prefetcher algorithm, compare the accuracy ratio with a threshold accuracy ratio, and determine whether to apply the first candidate prefetcher algorithm to the prefetcher module.

公开(公告)号：US10102134B2

公开(公告)日：2018-10-16

申请号：US15190231

申请日：2016-06-23

Applicant: Intel Corporation

Inventor： Zeshan A. Chishti ,  Christopher B. Wilkerson ,  Seth Pugsley ,  Peng-Fei Chuang ,  Robert L. Scott ,  Aamer Jaleel ,  Shih-Lien L. Lu ,  Kingsum Chow

IPC: G06F9/38 ,  G06F12/0862 ,  G06F3/06 ,  G06F13/40

Abstract: A processor includes a cache, a prefetcher module to select information according to a prefetcher algorithm, and a prefetcher algorithm selection module. The prefetcher algorithm selection module includes logic to select a candidate prefetcher algorithm determine and store memory addresses of predicted memory accesses of the candidate prefetcher algorithm when performed by the prefetcher module, determine cache lines accessed during memory operations, and evaluate whether the determined cache lines match the stored memory addresses. The prefetcher algorithm selection module further includes logic to adjust an accuracy ratio of the candidate prefetcher algorithm, compare the accuracy ratio with a threshold accuracy ratio, and determine whether to apply the first candidate prefetcher algorithm to the prefetcher module.

公开(公告)号：US10089207B2

公开(公告)日：2018-10-02

申请号：US14317485

申请日：2014-06-27

Applicant: Intel Corporation

Inventor： Shruthi A. Deshpande ,  Peng-Fei Chuang ,  Kingsum Chow

IPC: G06F11/34 ,  G06F9/48 ,  G06F9/50 ,  G06F11/30 ,  G06F11/36

Abstract: A computing device executes an application having a number of phases. The computing device collects performance data indicative of a number of performance attributes of the computing device during execution of the application. The performance attributes include page swap data, page fault data, and process queue data. The computing device merges data collected from a processor performance monitoring unit with data collected from an operating system of the computing device. The computing device partitions the performance data into a number of cluster models, applies a classification algorithm to each cluster model, and selects the cluster model with the lowest misclassification rate. The computing device associates each cluster of the cluster model to a phase of the software application. Compatible phases of software applications are scheduled based on the selected cluster model.

公开(公告)号：US09286224B2

公开(公告)日：2016-03-15

申请号：US14090056

申请日：2013-11-26

Applicant: Intel Corporation

Inventor： Seth H. Pugsley ,  Robert L. Scott ,  Zeshan A. Chishti ,  Peng-Fei Chuang ,  Khun Ban ,  Christopher B. Wilkerson ,  Shih-Lien L. Lu ,  Kingsum Chow

IPC: G06F12/08 ,  G06F9/45

CPC classification number: G06F12/0862 ,  G06F8/4442 ,  G06F12/0811 ,  G06F12/0897 ,  G06F2212/602 ,  Y02D10/13

Abstract: In an embodiment, a processor includes at least one core having one or more execution units, a first cache memory and a first cache control logic. The first cache control logic may be configured to generate a first prefetch request to prefetch first data, where this request is to be aborted if the first data is not present in a second cache memory coupled to the first cache memory. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括具有一个或多个执行单元的至少一个核，第一高速缓冲存储器和第一高速缓存控制逻辑。 第一高速缓存控制逻辑可以被配置为生成预取第一数据的第一预取请求，其中如果第一数据不存在于耦合到第一高速缓存存储器的第二高速缓冲存储器中，则该请求将被中止。 描述和要求保护其他实施例。