公开(公告)号：US20240387353A1

公开(公告)日：2024-11-21

申请号：US18320763

申请日：2023-05-19

Applicant: Intel Corporation

Inventor： Michael Langenbuch ,  Carla Moran Guizan ,  Mamatha Yakkegondi Virupakshappa ,  Roshini Sachithanandan ,  Philipp Riess ,  Jonathan Jensen ,  Peter Baumgartner ,  Georg Seidemann

IPC: H01L23/522 ,  H01L23/66

Abstract: Methods and apparatus are disclosed for implementing capacitors in semiconductor devices. An example semiconductor die includes a first dielectric material disposed between a first metal interconnect and a second metal interconnect; and a capacitor positioned within a via extending through the first dielectric material between the first and second metal interconnects, the capacitor including a second dielectric material disposed in the via between the first and second metal interconnects.

公开(公告)号：US20250006630A1

公开(公告)日：2025-01-02

申请号：US18342130

申请日：2023-06-27

Applicant: Intel Corporation

Inventor： Carla Moran Guizan ,  Peter Baumgartner ,  Thomas Wagner ,  Georg Seidemann ,  Michael Langenbuch ,  Mamatha Yakkegondi Virupakshappa ,  Jonathan Jensen ,  Roshini Sachithanandan ,  Philipp Riess

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/528 ,  H01L25/065

Abstract: Described herein are integrated circuit devices that include conductive structures formed by direct bonding of different components, e.g., direct bonding of two dies, or of a die to a wafer. The conductive structures are formed from a top metallization layer of each of the components. For example, elongated conductive structures at the top metallization layer may be patterned and bonded to form large interconnects for high-frequency and/or high-power signals. In another example, the bonded conductive structures may form radio frequency passive devices, such as inductors or transformers.

公开(公告)号：US20250006668A1

公开(公告)日：2025-01-02

申请号：US18342112

申请日：2023-06-27

Applicant: Intel Corporation

Inventor： Carla Moran Guizan ,  Peter Baumgartner ,  Michael Langenbuch ,  Mamatha Yakkegondi Virupakshappa ,  Jonathan Jensen ,  Roshini Sachithanandan ,  Philipp Riess

IPC: H01L23/66 ,  H01L23/528

Abstract: Waveguide structures are built into integrated circuit devices using standard processing steps for semiconductor device fabrication. A waveguide may include a base, a top, and two side walls. At least one of the walls (e.g., the base or the top) may be formed in a metal layer. The base or top may be patterned to provide a transition to a planar transmission line, such as a coplanar waveguide. The side walls may be formed using vias.

公开(公告)号：US11201151B2

公开(公告)日：2021-12-14

申请号：US16833094

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Richard Hudeczek ,  Philipp Riess ,  Richard Geiger ,  Peter Baumgartner

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06

Abstract: Embodiments disclosed herein include resonators, such as resonant fin transistors (RFTs). In an embodiment a resonator comprises a substrate, a set of contact fins over the substrate, a first contact proximate to a first end of the set of contact fins, and a second contact proximate to a second end of the set of contact fins. In an embodiment, the resonator further comprises a set of skip fins over the substrate and adjacent to the set of contact fins. In an embodiment, the resonator further comprises a gate electrode over the set of contact fins and the set of skip fins, wherein the gate electrode is between the first contact and the second contact.