公开(公告)号：US20250112125A1

公开(公告)日：2025-04-03

申请号：US18478222

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Ranjul Balakrishnan ,  Prabhat Ranjan ,  Prashant Dhirubhai Parmar ,  Naren Sreenivas Viswanathan ,  Russell Kevin Mortensen

IPC: H01L23/482 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: Bridges over metal voids in integrated circuit packages are disclosed. An example a substrate for an electronic circuit comprising a first conductive layer having an aperture extending through the first conductive layer, the aperture aligned with a contact pad, the first conductive layer including an arm extending from a first location on a perimeter of the aperture to a second location on the perimeter of the aperture, and a second conductive layer adjacent to the first conductive layer, the second conductive layer including a metal trace positioned adjacent to the arm, the arm between the metal trace and the contact pad.

公开(公告)号：US20230091395A1

公开(公告)日：2023-03-23

申请号：US17483670

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Mooi Ling Chang ,  Poh Boon Khoo ,  Chu Aun Lim ,  Min Suet Lim ,  Prabhat Ranjan

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/367 ,  H01L23/498 ,  H01L21/48 ,  H01L25/00

Abstract: Integrated circuit (IC) packages with On Package Memory (OPM) architectures are disclosed herein. An example IC package includes a substrate having a first side and a second side opposite the first side, a semiconductor die mounted on the first side of the substrate, and a die pad on the first side of the substrate. The die is electrically coupled to the die pad. The IC package also includes a memory pad on the first side of the substrate. The memory pad is to be electrically coupled to a memory mounted on the first side of the substrate. The IC package further includes a ball on the second side of the substrate, and a memory interconnect in the substrate electrically coupling the die pad, the memory pad, and the ball.

公开(公告)号：US20230317680A1

公开(公告)日：2023-10-05

申请号：US17707340

申请日：2022-03-29

Applicant: Intel Corporation

Inventor： Prabhat Ranjan ,  Boon Ping Koh ,  Min Suet Lim ,  Yew San Lim ,  Ranjul Balakrishnan ,  Omkar Karhade ,  Robert A. Stingel ,  Nitin Deshpande

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L24/49 ,  H01L24/48 ,  H01L2225/06562 ,  H01L2225/0651 ,  H01L2224/49176 ,  H01L2224/48097 ,  H01L2224/85986

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes one or more ribbon bond connections along with one or more wire bond connections. In one example, ribbon bond connections are shown, and are coupled to ground, and configured to provide a shielding effect to wire bond connections.

公开(公告)号：US20210315097A1

公开(公告)日：2021-10-07

申请号：US17353163

申请日：2021-06-21

Applicant: Intel Corporation

Inventor： Ranjul Balakrishnan ,  Roman Meltser ,  Prabhat Ranjan ,  Shivani R. Jain

IPC: H05K1/02

Abstract: In one embodiment, an apparatus includes a circuit board having a parallel bus with a first trace and a second trace, a first inductive coil coupled to the first trace, and a second inductive coil coupled to the second trace. The first and second inductive coils are arranged to inductively couple with one another to reduce cross talk effects in the parallel bus.