公开(公告)号：US09311239B2

公开(公告)日：2016-04-12

申请号：US13976313

申请日：2013-03-14

Applicant: Intel Corporation

Inventor： Niranjan Cooray ,  Steffen Kosinski ,  Rami May ,  Doron Gershon ,  Jaroslaw Topp ,  Varun Mohandru

IPC: G06F12/00 ,  G06F12/08 ,  G06F12/10

CPC classification number: G06F12/0811 ,  G06F12/0864 ,  G06F12/10 ,  G06F12/1027 ,  G06F12/1045 ,  G06F2212/283 ,  G06F2212/6032 ,  G06F2212/65 ,  G06F2212/681 ,  Y02D10/13

Abstract: A system and method to implement a tag structure for a cache memory that includes a multi-way, set-associative translation lookaside buffer. The tag structure may store vectors in an L1 tag array to enable an L1 tag lookup that has fewer bits per entry and consumes less power. The vectors may identify entries in a translation lookaside buffer tag array. When a virtual memory address associated with a memory access instruction hits in the translation lookaside buffer, the translation lookaside buffer may generate a vector identifying the set and the way of the translation lookaside buffer entry that matched. This vector may then be compared to a group of vectors stored in a set of the L1 tag arrays to determine whether the virtual memory address hits in the L1 cache.

Abstract translation: 一种用于实现高速缓冲存储器的标签结构的系统和方法，其包括多路组合关联翻译后备缓冲器。 标签结构可以将向量存储在L1标签阵列中，以便能够进行每个条目具有较少位的L1标签查找并消耗更少的功率。 向量可以标识翻译后备缓冲器标签阵列中的条目。 当与存储器访问指令相关联的虚拟存储器地址在翻译后备缓冲器中时，翻译后备缓冲器可以生成标识集合的向量和匹配的翻译后备缓冲器条目的方式。 然后将该向量与存储在一组L1标签阵列中的一组矢量进行比较，以确定虚拟存储器地址是否在L1高速缓存中命中。

公开(公告)号：US20150220436A1

公开(公告)日：2015-08-06

申请号：US13976313

申请日：2013-03-14

Applicant: Intel Corporation

Inventor： Niranjan Cooray ,  Steffen Kosinski ,  Rami May ,  Doron Gershon ,  Jaroslaw Topp ,  Varun Mohandru

IPC: G06F12/08 ,  G06F12/10

CPC classification number: G06F12/0811 ,  G06F12/0864 ,  G06F12/10 ,  G06F12/1027 ,  G06F12/1045 ,  G06F2212/283 ,  G06F2212/6032 ,  G06F2212/65 ,  G06F2212/681 ,  Y02D10/13

Abstract: A system and method to implement a tag structure for a cache memory that includes a multi-way, set-associative translation lookaside buffer. The tag structure may store vectors in an L1 tag array to enable an L1 tag lookup that has fewer bits per entry and consumes less power. The vectors may identify entries in a translation lookaside buffer tag array. When a virtual memory address associated with a memory access instruction hits in the translation lookaside buffer, the translation lookaside buffer may generate a vector identifying the set and the way of the translation lookaside buffer entry that matched. This vector may then be compared to a group of vectors stored in a set of the L1 tag arrays to determine whether the virtual memory address hits in the L1 cache.

Abstract translation: 一种用于实现高速缓冲存储器的标签结构的系统和方法，其包括多路组合关联翻译后备缓冲器。 标签结构可以将向量存储在L1标签阵列中，以便能够进行每个条目具有较少位的L1标签查找并消耗更少的功率。 向量可以标识翻译后备缓冲器标签阵列中的条目。 当与存储器访问指令相关联的虚拟存储器地址在翻译后备缓冲器中时，翻译后备缓冲器可以生成标识集合的向量和匹配的翻译后备缓冲器条目的方式。 然后将该向量与存储在一组L1标签阵列中的一组矢量进行比较，以确定虚拟存储器地址是否在L1高速缓存中命中。

公开(公告)号：US09195465B2

公开(公告)日：2015-11-24

申请号：US13729629

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Varun K. Mohandru ,  Fernando Latorre ,  Li-Gao Zei ,  Allan D. Knies ,  Rami May ,  Lutz Naethke

IPC: G06F9/38 ,  G06F12/08

CPC classification number: G06F9/3834 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3863 ,  G06F12/0815 ,  G06F2212/507

Abstract: Responsive to execution of a computer instruction in a current translation window, state indicators associated with a cache line accessed for the execution may be modified. The state indicators may include: a first indicator to indicate whether the computer instruction is a load instruction moved from a subsequent translation window into the current translation window, a second indicator to indicate whether the cache line is modified in a cache responsive to the execution of the computer instruction, a third indicator to indicate whether the cache line is speculatively modified in the cache responsive to the execution of the computer instruction, a fourth indicator to indicate whether the cache line is speculatively loaded by the computer instruction, a fifth indicator to indicate whether a core executing the computer instruction exclusively owns the cache line, and a sixth indicator to indicate whether the cache line is invalid.

Abstract translation: 响应于在当前翻译窗口中执行计算机指令，可以修改与为执行访问的高速缓存行相关联的状态指示符。 状态指示符可以包括：第一指示符，用于指示计算机指令是否是从后续转换窗口移动到当前转换窗口的加载指令;第二指示符，用于指示高速缓存行是否在缓存中被修改，响应于执行 计算机指令，第三指示符，用于指示高速缓存行是否响应于计算机指令的执行在高速缓存中被推测地修改;第四指示符，用于指示高速缓存行是否被计算机指令推测性加载;第五指示符，用于指示 执行计算机指令的核心是否独占拥有高速缓存行，以及指示高速缓存行是否无效的第六指示符。

公开(公告)号：US09009413B2

公开(公告)日：2015-04-14

申请号：US13724848

申请日：2012-12-21

Applicant: Intel Corporation

Inventor： Varun K. Mohandru ,  Fernando Latorre ,  Niranjan L. Cooray ,  Pedro Lopez ,  Naveen Neelakantam ,  Li-Gao Zei ,  Rami May ,  Jaroslaw Topp ,  Thomas Gaertner

IPC: G06F12/08 ,  G11C7/10 ,  G06F12/10

CPC classification number: G11C7/1072 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/1036

Abstract: A processor includes a processor core including an execution unit to execute instructions, and a cache memory. The cache memory includes a controller to update each of a plurality of stale indicators in response to a lazy flush instruction. Each stale indicator is associated with respective data, and each updated stale indicator is to indicate that the respective data is stale. The cache memory also includes a plurality of cache lines. Each cache line is to store corresponding data and a foreground tag that includes a respective virtual address associated with the corresponding data, and that includes the associated stale indicator. Other embodiments are described as claimed.

Abstract translation: 处理器包括处理器核心，其包括执行指令的执行单元和高速缓冲存储器。 高速缓冲存储器包括控制器，以响应于惰性冲洗指令来更新多个陈旧指示器中的每一个。 每个陈旧的指示符与相应的数据相关联，每个更新的陈旧指示符指示相应的数据是否过时。 高速缓冲存储器还包括多条高速缓存行。 每个高速缓存行将存储对应的数据和前景标签，其包括与对应的数据相关联的相应的虚拟地址，并且其包括相关联的陈旧指示符。 其他实施例被描述为所要求保护的。