公开(公告)号：US11462527B2

公开(公告)日：2022-10-04

申请号：US16049696

申请日：2018-07-30

Applicant: Intel Corporation

Inventor： Kumar Abhishek Singh ,  Zhaozhi Li ,  Thomas J. Debonis ,  Robert Nickerson ,  Rees Winters

IPC: H01L23/48 ,  H01L25/18 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/544 ,  H01L25/00

Abstract: Embodiments disclosed herein include an electronics package. In an embodiment, the electronics package comprises a package substrate and a die on the package substrate. In an embodiment, a mold layer is positioned over the package substrate. In an embodiment, the electronics package further comprises through-mold interconnects through the mold layer, and a trench that extends at least partially into the mold layer.

公开(公告)号：US11705383B2

公开(公告)日：2023-07-18

申请号：US16550773

申请日：2019-08-26

Applicant: Intel Corporation

Inventor： Robert M. Nickerson ,  Rees Winters ,  Purushotham Kaushik Muthur Srinath

IPC: H01L23/31 ,  H01L23/48

CPC classification number: H01L23/481 ,  H01L23/315

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, a first die electrically coupled to the package substrate, and a mold layer over the package substrate and around the first die. In an embodiment, the electronic package further comprises a through mold opening through the mold layer, and a through mold interconnect (TMI) in the through mold opening, wherein a center of the TMI is offset from a center of the through mold opening.