公开(公告)号：US20230197677A1

公开(公告)日：2023-06-22

申请号：US17557622

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Stephen R. Van Doren ,  Ritu Gupta ,  Gerald S. Pasdast ,  Robert J. Munoz ,  Shawna M. Liff

IPC: H01L25/065

CPC classification number: H01L25/0652 ,  H01L2225/06548

Abstract: A microelectronic assembly is provided comprising: a first plurality of integrated circuit (IC) dies arranged in an array of rows and columns in a first layer; and a second plurality of IC dies in a second layer not coplanar with the first layer. A first IC die in the first plurality is differently sized than surrounding IC dies in the first plurality, and a second IC die in the second plurality coupled to the first IC die comprises at least one of: a repeater circuitry and a fanout structure in an electrical pathway coupling the first IC die with an adjacent IC die in the first plurality.

公开(公告)号：US20240168890A1

公开(公告)日：2024-05-23

申请号：US18058401

申请日：2022-11-23

Applicant: Intel Corporation

Inventor： Chitra Natarajan ,  Aneesh Aggarwal ,  Ritu Gupta ,  Niall Declan McDonnell ,  Kapil Sood ,  Youngsoo Choi ,  Asad Khan ,  Lokpraveen Mosur ,  Subhiksha Ravisundar ,  George Leonard Tkachuk

IPC: G06F12/12

CPC classification number: G06F12/12 ,  G06F2212/1021

Abstract: A processor package comprises a caching agent that is operable to respond to a first sequence of direct-to-cache (DTC) write misses to a partition in a set in a cache by writing data from those write misses to the partition. When the partition comprises W ways, the caching agent is operable to write data from those write misses to all W ways in the partition. After writing data from those write misses to the partition, and before any data from the partition in the set has been read, the caching agent is operable to receive a second sequence of DTC write misses to the partition, and in response, complete those write misses while retaining the data from the first sequence in at least W-1 of the ways in the partition. Other embodiments are described and claimed.

公开(公告)号：US11263143B2

公开(公告)日：2022-03-01

申请号：US15720231

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Ritu Gupta ,  Aravindh V. Anantaraman ,  Stephen R. Van Doren ,  Ashok Jagannathan

IPC: G06F12/00 ,  G06F12/0884 ,  G06F13/42

Abstract: A fabric controller is provided for a coherent accelerator fabric. The coherent accelerator fabric includes a host interconnect, a memory interconnect, and an accelerator interconnect. The host interconnect communicatively couples to a host device. The memory interconnect communicatively couples to an accelerator memory. The accelerator interconnect communicatively couples to an accelerator having a last-level cache (LLC). An LLC controller is provided that is configured to provide a bias check for memory access operations on the fabric.

公开(公告)号：US20190102311A1

公开(公告)日：2019-04-04

申请号：US15720231

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Ritu Gupta ,  Aravindh V. Anantaraman ,  Stephen R. Van Doren ,  Ashok Jagannathan

IPC: G06F12/0884 ,  G06F13/42

Abstract: A fabric controller to provide a coherent accelerator fabric, including: a host interconnect to communicatively couple to a host device; a memory interconnect to communicatively couple to an accelerator memory; an accelerator interconnect to communicatively couple to an accelerator having a last-level cache (LLC); and an LLC controller configured to provide a bias check for memory access operations.

公开(公告)号：US20230367492A1

公开(公告)日：2023-11-16

申请号：US17741386

申请日：2022-05-10

Applicant: Intel Corporation

Inventor： Ritu Gupta ,  Anand K. Enamandram

IPC: G06F3/06

CPC classification number: G06F3/0629 ,  G06F3/0611 ,  G06F3/0673

Abstract: Embodiments of apparatuses, methods, and systems for flexible provisioning of coherent memory address decoders in hardware are disclosed. In an embodiment, an apparatus includes a plurality of address decoders and a plurality of configuration storage locations. Each of the configuration storage locations corresponds to one of the plurality of address decoders to configure the corresponding one of the plurality of address decoders to decode based on a corresponding one of a plurality of decode rules. Each of the plurality of configuration storage locations is allocated to one of a plurality of memory tiers.

公开(公告)号：US20230315632A1

公开(公告)日：2023-10-05

申请号：US17711471

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Philip Abraham ,  Stephen Van Doren ,  Ritu Gupta ,  Andrew Herdrich

IPC: G06F12/0811 ,  G06F12/0846 ,  G06F12/084

CPC classification number: G06F12/0811 ,  G06F12/0846 ,  G06F12/084

Abstract: Techniques and mechanisms to facilitate access to a cache based on a dual basis partition scheme. In an embodiment, a first one or more registers of a processor provide information which describes multiple set-wise partitions of a cache. A second one or more registers of the processor provides additional information which describes multiple way-wise partitions of the cache. A virtual cache is defined as that region of the cache which is both in a particular set-wise partition, and in a particular way-wise partition. In another embodiment, a cache agent of the processor performs operations, based on the set-wise partitioning and the way-wise partitioning, to determine a mapping of one address—which is provided in a memory access request, and which indicates a location in one virtual cache—to another address which indicates another location in a different virtual cache.

公开(公告)号：US20230086222A1

公开(公告)日：2023-03-23

申请号：US17478828

申请日：2021-09-17

Applicant: Intel Corporation

Inventor： Anand K. Enamandram ,  Ritu Gupta

IPC: G06F13/38 ,  G06F13/42 ,  G06F13/40 ,  G06F13/16 ,  G06F9/46

Abstract: Methods and apparatus relating to a scalable address decoding scheme for Compute Express Link™ or CXL™ Type-2 devices with programmable interleave granularity are described. In an embodiment, configurator logic circuitry determines an interleave granularity and an address range size for a plurality of devices coupled to a socket of a processor. A single System Address Decoder (SAD) rule for two or more of the plurality of the devices coupled to the socket of the processor is stored in memory. A memory access transaction directed at a first device from the plurality of devices is routed to the first device in accordance with the SAD rule. Other embodiments are also disclosed and claimed.

公开(公告)号：US11663135B2

公开(公告)日：2023-05-30

申请号：US17555789

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Ritu Gupta ,  Aravindh V. Anantaraman ,  Stephen R. Van Doren ,  Ashok Jagannathan

IPC: G06F12/00 ,  G06F12/0884 ,  G06F13/42

CPC classification number: G06F12/0884 ,  G06F13/4282 ,  G06F2212/621 ,  G06F2213/0026

Abstract: A fabric controller to provide a coherent accelerator fabric, including: a host interconnect to communicatively couple to a host device; a memory interconnect to communicatively couple to an accelerator memory; an accelerator interconnect to communicatively couple to an accelerator having a last-level cache (LLC); and an LLC controller configured to provide a bias check for memory access operations.

公开(公告)号：US20220197803A1

公开(公告)日：2022-06-23

申请号：US17132216

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Ritu Gupta ,  Robert Blankenship

IPC: G06F12/0831 ,  G06F12/0891 ,  G06F12/0811 ,  G06F12/0813

Abstract: In one embodiment, a system includes an (input/output) I/O domain and a compute domain. The I/O domain includes an I/O agent and a I/O domain caching agent. The compute domain includes a compute domain caching agent and a compute domain cache hierarchy. The I/O agent issues an ownership request to the compute domain caching agent to obtain ownership of a cache line in the compute domain cache hierarchy. In response to the ownership request, the compute domain caching agent places the cache line in the compute domain cache hierarchy in a placeholder state. The placeholder state reserves the cache line for performance of a write operation by the I/O agent. The compute domain caching agent writes data received from the I/O agent to the cache line in the compute domain cache hierarchy and transitions the state of the cache line out of the placeholder state.

公开(公告)号：US20220114105A1

公开(公告)日：2022-04-14

申请号：US17555789

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Ritu Gupta ,  Aravindh V. Anantaraman ,  Stephen R. Van Doren ,  Ashok Jagannathan

IPC: G06F12/0884 ,  G06F13/42

Abstract: A fabric controller to provide a coherent accelerator fabric, including: a host interconnect to communicatively couple to a host device; a memory interconnect to communicatively couple to an accelerator memory; an accelerator interconnect to communicatively couple to an accelerator having a last-level cache (LLC); and an LLC controller configured to provide a bias check for memory access operations.