公开(公告)号：US20250113529A1

公开(公告)日：2025-04-03

申请号：US18375082

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Jessica PANELLA ,  Manjunath CHINNAPPAMUDALIAR RAJAGOPAL ,  SHARANYA SUBRAMANIAM ,  Robert JOACHIM ,  Dario FARIAS

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Integrated circuit structures having fin cuts, and methods of fabricating integrated circuit structures having fin cuts, are described. For example, an integrated circuit structure includes a first fin structure or nanowire stack and sub-fin pairing separated from a second fin structure or nanowire stack and sub-fin pairing by a cut, wherein an end of the first fin structure or nanowire stack and sub-fin pairing is facing toward an end of the second fin structure or nanowire stack and sub-fin pairing. A first gate structure is overlying the first fin structure or nanowire stack and sub-fin pairing, and a second gate structure is overlying the second fin structure or nanowire stack and sub-fin pairing. A first isolation structure is overlying the end of the first fin structure or nanowire stack and sub-fin pairing and laterally spaced apart from the first gate structure, and a second isolation structure is overlying the end of the second fin structure or nanowire stack and sub-fin pairing and laterally spaced apart from the second gate structure.

公开(公告)号：US20220390990A1

公开(公告)日：2022-12-08

申请号：US17339001

申请日：2021-06-04

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Mohammad HASAN ,  Charles H. WALLACE ,  Tahir GHANI ,  Robert JOACHIM ,  Shengsi LIU ,  Tsuan-Chung CHANG

IPC: G06F1/18 ,  H05K1/11 ,  G06F1/16

Abstract: Spacer self-aligned via structures for gate contact or trench contact are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. The integrated circuit structure also includes a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers between adjacent ones of the plurality of gate structures and the plurality of conductive trench contact structures, wherein the plurality of dielectric spacers protrudes above the plurality of gate structures and above the plurality of conductive trench contact structures. A conductive structure is in direct contact with one of the plurality of gate structures or with one of the plurality of conductive trench contact structures.

公开(公告)号：US20240113109A1

公开(公告)日：2024-04-04

申请号：US17958291

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Robert JOACHIM ,  Shengsi LIU ,  Hongqian SUN ,  Tahir GHANI

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/00

CPC classification number: H01L27/088 ,  H01L21/8234 ,  H01L23/564

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for forming a plug between two gates within a transistor layer of a semiconductor device. In embodiments, the plug includes a cap at a top of the plug and a liner surrounding at least a portion of the cap, and a base below the cap and the liner. The cap may include a metal. A top of the cap may be even with, or substantially even with, the top of the two gates. The plug may provide a more even surface at a top of a transistor layer where the plug fills in for a gate cut. Other embodiments may be described and/or claimed.

公开(公告)号：US20240105597A1

公开(公告)日：2024-03-28

申请号：US17950926

申请日：2022-09-22

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Robert JOACHIM ,  Shengsi LIU ,  Tahir GHANI ,  Charles H. WALLACE

IPC: H01L23/528 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L23/53238

Abstract: Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a plurality of conductive lines along a same direction, one of the conductive lines having a break therein. An inter-layer dielectric (ILD) structure has portions between adjacent ones of the plurality of conductive lines and has a dielectric plug portion in a location of the break in the one of the conductive lines. The dielectric plug portion of the ILD structure is continuous with one or more of the portions of the ILD structure between adjacent ones of the plurality of conductive lines. The dielectric plug portion of the ILD structure has an inwardly tapering profile from top to bottom.

公开(公告)号：US20240395815A1

公开(公告)日：2024-11-28

申请号：US18200967

申请日：2023-05-23

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Manish CHANDHOK ,  Tsuan-Chung CHANG ,  Robert JOACHIM ,  Peter NGUYEN ,  Lily MAO ,  Erik SKIBINSKI

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: Integrated circuit structures having metal-containing fin isolation regions are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires over a first sub-fin. A gate structure is over the vertical stack of horizontal nanowires and on the first sub-fin. A dielectric structure is laterally spaced apart from the gate structure. The dielectric structure is not over a channel structure but is on a second sub-fin. A gate cut is between the gate structure and the dielectric structure. A dielectric gate cut plug is in the gate cut. The dielectric gate plug includes a metal-containing dielectric material.

公开(公告)号：US20240105802A1

公开(公告)日：2024-03-28

申请号：US17953085

申请日：2022-09-26

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Marie CONTE ,  Charles H. WALLACE ,  Robert JOACHIM ,  Shengsi LIU ,  Saurabh ACHARYA ,  Nidhi KHANDELWAL ,  Kyle T. HORAK ,  Robert ROBINSON ,  Brandon PETERS

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/7854 ,  H01L29/78696

Abstract: Integrated circuit structures having gate cut plugs removed from trench contacts, and methods of fabricating integrated circuit structures having gate cut plugs removed from trench contacts, are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires. A gate electrode is over the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A gate cut plug extends through the gate electrode and the dielectric sidewall spacer. The gate cut plug extends into but not entirely through the conductive trench contact.

公开(公告)号：US20220415791A1

公开(公告)日：2022-12-29

申请号：US17357773

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Tsuan-Chung CHANG ,  Michael James MAKOWSKI ,  Benjamin KRIEGEL ,  Robert JOACHIM ,  Desalegne B. TEWELDEBRHAN ,  Charles H. WALLACE ,  Tahir GHANI ,  Mohammad HASAN

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

Abstract: Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a dielectric material structure having a trench therein. A conductive interconnect line in the trench, the conductive interconnect line having a length and a width, the width having a cross-sectional profile, wherein the cross-sectional profile of the width of the conductive interconnect line has a bottom lateral width, a mid-height lateral width, and a top lateral width, and wherein the mid-height lateral width is greater than the bottom lateral width, and the mid-height lateral width is greater than the top lateral width.