公开(公告)号：US20230100106A1

公开(公告)日：2023-03-30

申请号：US17483904

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Prashant Dewan ,  Siddhartha Chhabra ,  Robert Royer, JR. ,  Baiju Patel

IPC: G06F12/14 ,  G06F3/06

Abstract: In one embodiment, an apparatus includes: an access control circuit to receive a memory transaction directed to a storage, the memory transaction having a requester ID and a key ID; a first memory to store an access control table, the access control table having a plurality of entries each to store a requester ID and at least one key ID; and a cryptographic circuit coupled to the access control circuit, the cryptographic circuit to perform a cryptographic operation on data associated with the memory transaction based at least in part on the key ID. The apparatus may be implemented as an inline engine coupled between the storage and an accelerator, the inline engine to provide decrypted data to the accelerator, the storage to store encrypted data. Other embodiments are described and claimed.

公开(公告)号：US20220171551A1

公开(公告)日：2022-06-02

申请号：US17673162

申请日：2022-02-16

Applicant: Intel Corporation

Inventor： Virendra Vikramsinh Adsure ,  Deepak Gandiga Shivakumar ,  Robert Royer, JR.

IPC: G06F3/06

Abstract: Systems, apparatuses, and methods may provide for optimizing the available memory in a power conscious compute platform. For example, a semiconductor apparatus includes logic to communicate with a system memory to divide a plurality of memory channels into functional channels and performance channels. The functional channels are in an active power state during a boot process and the performance channels are in an idle power state during the boot process. The semiconductor apparatus includes logic to track memory usage and bring the performance channels out of the idle power state and into the active power state in response to the tracked memory usage.

公开(公告)号：US20190042155A1

公开(公告)日：2019-02-07

申请号：US15978766

申请日：2018-05-14

Applicant: Intel Corporation

Inventor： Eng Hun Ooi ,  Shrinivas Venkatraman ,  Kuan Hua Tan ,  Ang Li ,  Sahar Khalili ,  Su Wei Lim ,  Robert Royer, JR.

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/42 ,  G06F12/06

Abstract: Systems, apparatuses and methods may provide for technology to add non-address metadata to a memory address field of a transaction layer packet (TLP), wherein the non-address metadata includes one or more vendor-specific attributes. Additionally, the technology may coordinate between a transmitter and a receiver to prevent the TLP from violating an address boundary constraint associated with an interface. In one example, the address boundary constraint prohibits an address and length combination of the TLP from crossing a 4-KB boundary.