公开(公告)号：US20210117190A1

公开(公告)日：2021-04-22

申请号：US17134249

申请日：2020-12-25

Applicant: Intel Corporation

Inventor： Toby Opferman ,  Russell C. Arnold ,  Vedvyas Shanbhogue

IPC: G06F9/30 ,  G06F9/455

Abstract: Embodiments of processors, methods, and systems for a processor core supporting processor identification instruction spoofing are described. In an embodiment, a processor includes an instruction decoder and processor identification instruction spoofing logic. The processor identification spoofing logic is to respond to a processor identification instruction by reporting processor identification information from a processor identification spoofing data structure. The processor identification spoofing data structure is to include processor identification information of one or more other processors.

公开(公告)号：US11507368B2

公开(公告)日：2022-11-22

申请号：US17134249

申请日：2020-12-25

Applicant: Intel Corporation

Inventor： Toby Opferman ,  Russell C. Arnold ,  Vedvyas Shanbhogue

IPC: G06F9/30 ,  G06F9/455

Abstract: Embodiments of processors, methods, and systems for a processor core supporting processor identification instruction spoofing are described. In an embodiment, a processor includes an instruction decoder and processor identification instruction spoofing logic. The processor identification spoofing logic is to respond to a processor identification instruction by reporting processor identification information from a processor identification spoofing data structure. The processor identification spoofing data structure is to include processor identification information of one or more other processors.

公开(公告)号：US11055094B2

公开(公告)日：2021-07-06

申请号：US16453531

申请日：2019-06-26

Applicant: Intel Corporation

Inventor： Toby Opferman ,  Russell C. Arnold ,  Vedvyas Shanbhogue ,  Michael W. Chynoweth

IPC: G06F9/30

Abstract: Disclosed embodiments relate to improved heterogeneous CPUID spoofing for remote processors. In one example, a system includes multiple processors, including a first processor including configuration circuitry to enable remote processor identification (ID) spoofing; fetch circuitry to fetch an instruction; decode circuitry to decode the instruction having fields to specify an opcode and a context, the opcode indicating execution circuitry is to: when remote processor ID spoofing is enabled, access a processor ID spoofing data structure storing processor ID information for each of the plurality of processors, and report processor ID information for a processor identified by the context; and, when remote processor ID spoofing is not enabled, report processor ID information for the first processor; and execution circuitry to execute the instruction as per the opcode.

公开(公告)号：US10949207B2

公开(公告)日：2021-03-16

申请号：US16147702

申请日：2018-09-29

Applicant: Intel Corporation

Inventor： Toby Opferman ,  Russell C. Arnold ,  Vedvyas Shanbhogue

IPC: G06F9/30 ,  G06F9/455

Abstract: Embodiments of processors, methods, and systems for a processor core supporting a heterogenous system instruction set architecture are described. In an embodiment, a processor includes an instruction decoder and an exception generation circuit. The exception generation circuit is to, in response to the instruction decoder receiving an unsupported instruction, generate an exception and report an instruction classification value of the unsupported instruction.

公开(公告)号：US20190042258A1

公开(公告)日：2019-02-07

申请号：US16147702

申请日：2018-09-29

Applicant: Intel Corporation

Inventor： Toby Opferman ,  Russell C. Arnold ,  Vedvyas Shanbhogue

IPC: G06F9/30 ,  G06F9/455

Abstract: Embodiments of processors, methods, and systems for a processor core supporting a heterogenous system instruction set architecture are described. In an embodiment, a processor includes an instruction decoder and an exception generation circuit. The exception generation circuit is to, in response to the instruction decoder receiving an unsupported instruction, generate an exception and report an instruction classification value of the unsupported instruction.