公开(公告)号：US11409572B2

公开(公告)日：2022-08-09

申请号：US16586706

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Toby Opferman ,  Eliezer Weissmann ,  Robert Valentine ,  Russell Cameron Arnold

IPC: G06F9/50 ,  G06F9/38 ,  G06F9/48 ,  G06F9/30 ,  G06F9/448

Abstract: The present disclosure relates to a processor that includes one or more processing elements associated with one or more instruction set architectures. The processor is configured to receive a request from an application executed by a first processing element of the one or more processing elements to enable a feature associated with an instruction set architecture. Additionally, the processor is configured to enable the application to utilize the feature without a system call occurring when the feature is associated with an instruction set architecture associated with the first processing element.

公开(公告)号：US11734079B2

公开(公告)日：2023-08-22

申请号：US17882175

申请日：2022-08-05

Applicant: Intel Corporation

Inventor： Toby Opferman ,  Eliezer Weissmann ,  Robert Valentine ,  Russell Cameron Arnold

IPC: G06F9/50 ,  G06F9/38 ,  G06F9/48 ,  G06F9/30 ,  G06F9/448

CPC classification number: G06F9/5055 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/3885 ,  G06F9/449 ,  G06F9/4806 ,  G06F9/4881 ,  G06F9/5044

Abstract: The present disclosure relates to a processor that includes one or more processing elements associated with one or more instruction set architectures. The processor is configured to receive a request from an application executed by a first processing element of the one or more processing elements to enable a feature associated with an instruction set architecture. Additionally, the processor is configured to enable the application to utilize the feature without a system call occurring when the feature is associated with an instruction set architecture associated with the first processing element.

公开(公告)号：US20220374278A1

公开(公告)日：2022-11-24

申请号：US17882175

申请日：2022-08-05

Applicant: Intel Corporation

Inventor： Toby Opferman ,  Eliezer Weissmann ,  Robert Valentine ,  Russell Cameron Arnold

IPC: G06F9/50 ,  G06F9/38 ,  G06F9/48 ,  G06F9/30 ,  G06F9/448

Abstract: The present disclosure relates to a processor that includes one or more processing elements associated with one or more instruction set architectures. The processor is configured to receive a request from an application executed by a first processing element of the one or more processing elements to enable a feature associated with an instruction set architecture. Additionally, the processor is configured to enable the application to utilize the feature without a system call occurring when the feature is associated with an instruction set architecture associated with the first processing element.

公开(公告)号：US20210096908A1

公开(公告)日：2021-04-01

申请号：US16586706

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Toby Opferman ,  Eliezer Weissmann ,  Robert Valentine ,  Russell Cameron Arnold

IPC: G06F9/48 ,  G06F9/38

Abstract: The present disclosure relates to a processor that includes one or more processing elements associated with one or more instruction set architectures. The processor is configured to receive a request from an application executed by a first processing element of the one or more processing elements to enable a feature associated with an instruction set architecture. Additionally, the processor is configured to enable the application to utilize the feature without a system call occurring when the feature is associated with an instruction set architecture associated with the first processing element.