公开(公告)号：US20200034061A1

公开(公告)日：2020-01-30

申请号：US16585801

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Sahar KHALILI ,  Zvika GREENFIELD ,  Sowmiya JAYACHANDRAN ,  Robert J. ROYER, JR. ,  Dimpesh PATEL

IPC: G06F3/06 ,  G06F12/0862

Abstract: A multilevel memory subsystem includes a persistent memory device that can access data chunks sequentially or randomly to improve read latency, or can prefetch data blocks to improve read bandwidth. A media controller dynamically switches between a first read mode of accessing data chunks sequentially or randomly and a second read mode of prefetching data blocks. The media controller switches between the first and second read modes based on a number of read commands pending in a command queue.

公开(公告)号：US20200278883A1

公开(公告)日：2020-09-03

申请号：US16878064

申请日：2020-05-19

Applicant: Intel Corporation

Inventor： Kuan Hua TAN ,  Sahar KHALILI ,  Eng Hun OOI ,  Shrinivas VENKATRAMAN ,  Dimpesh PATEL

IPC: G06F9/46 ,  G06F9/54 ,  G06F13/16 ,  G06F13/42 ,  G06F13/38 ,  G06F11/30

Abstract: A multilevel memory system includes a nonvolatile memory (NVM) device with an NVM media having a media write unit that is different in size than a host write unit of a host controller of the system that has the multilevel memory system. The memory device includes a media controller that controls writes to the NVM media. The host controller sends a write transaction to the media controller. The write transaction can include the write data in host write units, while the media controller will commit data in media write units to the NVM media. The media controller can send a transaction message to indicate whether the write data for the write transaction was successfully committed to the NVM media.

公开(公告)号：US20210097004A1

公开(公告)日：2021-04-01

申请号：US17122152

申请日：2020-12-15

Applicant: Intel Corporation

Inventor： Suresh NAGARAJAN ,  Scott CRIPPIN ,  Sahar KHALILI ,  Shankar NATARAJAN ,  Romesh TRIVEDI

IPC: G06F12/1009

Abstract: A solid state drive with a Logical To Physical (L2P) indirection table stored in a persistent memory is provided. The L2P indirection table has a plurality of entries, each entry to store a physical block address in the block addressable memory assigned to a logical block address. The solid state drive including solid state drive controller circuitry communicatively coupled to the persistent memory and the block addressable memory. The solid state drive controller circuitry including a volatile memory to store a logical to physical address indirection table cache and circuitry to monitor the logical to physical address indirection table cache and to write dirty logical to physical entries in the logical to physical address indirection table cache to the logical to physical address indirection table in the persistent memory.