公开(公告)号：US11275663B2

公开(公告)日：2022-03-15

申请号：US16896070

申请日：2020-06-08

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Nimrod Angel ,  Ameya Ambardekar ,  Sapumal Wijeratne ,  Vikas Vij ,  Tod Schiff ,  Alexander Uan-Zo-Li

IPC: G06F1/3296 ,  G06F11/30 ,  G06F11/07 ,  G06F9/30 ,  G06F9/4401

Abstract: A dedicated pin of a processor or system-on-chip (SoC) is used to indicate whether power level (e.g., charge, voltage, and/or current) of a battery falls below a threshold. The threshold can be predetermined or programmable. The battery is used to provide power to the processor and/or SoC. Upon determining that the power level of the battery falls below the threshold, the processor by-passes the conventional process of entering low performance or power mode, and directly throttles voltage and/or operating frequency of the processor. This allows the processor to continue to operate at low battery power. The fast transition (e.g., approximately 10 μS) from an active state to a low performance or power mode, in accordance with a logic level of the voltage on the dedicated pin, reduces decoupling capacitor design requirements, and makes it possible for the processor to adapt higher package power control settings (e.g., PL4).

公开(公告)号：US20210382805A1

公开(公告)日：2021-12-09

申请号：US16896070

申请日：2020-06-08

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Nimrod Angel ,  Ameya Ambardekar ,  Sapumal Wijeratne ,  Vikas Vij ,  Tod Schiff ,  Alexander Uan-Zo-Li

IPC: G06F11/30 ,  G06F11/07 ,  G06F1/3296 ,  G06F9/4401 ,  G06F9/30

Abstract: A dedicated pin of a processor or system-on-chip (SoC) is used to indicate whether power level (e.g., charge, voltage, and/or current) of a battery falls below a threshold. The threshold can be predetermined or programmable. The battery is used to provide power to the processor and/or SoC. Upon determining that the power level of the battery falls below the threshold, the processor by-passes the conventional process of entering low performance or power mode, and directly throttles voltage and/or operating frequency of the processor. This allows the processor to continue to operate at low battery power. The fast transition (e.g., approximately 10 μS) from an active state to a low performance or power mode, in accordance with a logic level of the voltage on the dedicated pin, reduces decoupling capacitor design requirements, and makes it possible for the processor to adapt higher package power control settings (e.g., PL4).

公开(公告)号：US12235792B2

公开(公告)日：2025-02-25

申请号：US18128852

申请日：2023-03-30

Applicant: Intel Corporation

Inventor： Jianwei Dai ,  Somvir Singh Dahiya ,  Mahesh Kumar P ,  Stephen H. Gunther ,  Sapumal Wijeratne ,  Mark Gallina

IPC: G06F9/50 ,  G06F1/324 ,  G06F9/48 ,  G06F15/78

Abstract: An apparatus and method for temperature-constrained frequency control and scheduling. For example, one embodiment of a processor comprises: a plurality of cores; power management circuitry to control a frequency of each core of the plurality of cores based, at least in part, on a temperature associated with one or more cores of the plurality of cores, the power management circuitry comprising: a temperature limit-driven frequency controller to determine a first frequency limit value based on a temperature of a corresponding core reaching a first threshold; frequency prediction hardware logic to predict a temperature-constrained frequency of the corresponding core based on the first frequency limit value and an initial frequency limit value; and performance determination hardware logic to determine a new performance value for the corresponding core based on the temperature-constrained frequency, the new performance value to be provided to a task scheduler.

公开(公告)号：US20250060803A1

公开(公告)日：2025-02-20

申请号：US18474385

申请日：2023-09-26

Applicant: Intel Corporation

Inventor： Sapumal Wijeratne ,  Stephen H. Gunther ,  Rene Barrientos Barrientos ,  Joseph Alberts ,  Preeti Agarwal ,  Chee Lim Nge ,  Jorge Rodriguez

IPC: G06F1/3209

Abstract: In one example, an apparatus comprises a first intellectual property (IP) circuit to execute operations on data and a power controller. The power controller is to: receive a boost value that is based at least in part on one or more characteristics of a power supply; determine a boosted maximum power level based at least in part on the boost value and a legacy maximum power level; and provide a boosted maximum power budget for the first IP circuit based at least in part on the boosted maximum power level. The first IP circuit, in response to an input voltage violation signal, is to reactively reduce power consumption equal to or below a legacy maximum power budget for the first IP circuit lower than the boosted maximum power budget. Other embodiments are described and claimed.