中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

10 records (took 0.06 seconds)

    CHIPLET ARCHITECTURE FOR LATE BIND SKU FUNGIBILITY
    6.
    发明公开
    CHIPLET ARCHITECTURE FOR LATE BIND SKU FUNGIBILITY 审中-公开

    公开(公告)号：US20230305978A1

    公开(公告)日：2023-09-28

    申请号：US17702271

    申请日：2022-03-23

    Applicant: Intel Corporation

    Inventor： Mark C. Davis ,  Hong Jiang ,  Satish Damaraju

    IPC: G06F13/40

    CPC classification number: G06F13/4022 ,  G06F13/4009 ,  G06F13/4068

    Abstract: Described herein is a modular parallel processor comprising an active base die including hardware logic, interconnect logic, and a plurality of chiplet slots and a plurality of chiplets vertically stacked on the active base die and coupled with the plurality of chiplet slots of the active base die. The plurality of chiplets is interchangeable during assembly of the modular parallel processor and include a group of hardware logic chiplets having a plurality of different functional units and a group of memory chiplets having a plurality of different memory devices. The hardware logic chiplets and the memory chiplets interconnect via the interconnect logic within the active base die.

    LOW-POWER SINGLE-EDGE TRIGGERED FLIP-FLOP, AND TIME BORROWING INTERNALLY STITCHED FLIP-FLOP
    8.
    发明申请
    LOW-POWER SINGLE-EDGE TRIGGERED FLIP-FLOP, AND TIME BORROWING INTERNALLY STITCHED FLIP-FLOP 有权

    公开(公告)号：US20210281250A1

    公开(公告)日：2021-09-09

    申请号：US16813558

    申请日：2020-03-09

    Applicant: Intel Corporation

    Inventor： Steven Hsu ,  Amit Agarwal ,  Simeon Realov ,  Satish Damaraju ,  Ram Krishnamurthy

    IPC: H03K3/037 ,  G06F3/06 ,  G01R31/3177 ,  G06F1/06

    Abstract: A new family of shared clock single-edge triggered flip-flops that reduces a number of internal clock devices from 8 to 6 devices to reduce clock power. The static pass-gate master-slave flip-flop has no performance penalty compared to the flip-flops with 8 clock devices thus enabling significant power reduction. The flip-flop intelligently maintains the same polarity between the master and slave stages which enables the sharing of the master tristate and slave state feedback clock devices without risk of charge sharing across all combinations of clock and data toggling. Because of this, the state of the flip-flop remains undisturbed, and is robust across charge sharing noise. A multi-bit time borrowing internal stitched flip-flop is also described, which enables internal stitching of scan in a high performance time-borrowing flip-flop without incurring increase in layout area.

Patent Agency Ranking