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    USER-LEVEL EXCEPTION-BASED INVOCATION OF SOFTWARE INSTRUMENTATION HANDLERS
    2.
    发明公开
    USER-LEVEL EXCEPTION-BASED INVOCATION OF SOFTWARE INSTRUMENTATION HANDLERS 审中-公开

    公开(公告)号：US20240095063A1

    公开(公告)日：2024-03-21

    申请号：US17949353

    申请日：2022-09-21

    Applicant: Intel Corporation

    Inventor： Michael LeMay ,  Scott Constable ,  David M. Durham

    IPC: G06F9/48

    CPC classification number: G06F9/4818

    Abstract: Techniques for improving exception-based invocation of instrumentation handler programs include executing, by a processor, an interrupt instruction of an instrumented program, the interrupt instruction having an interrupt number; searching for the interrupt number in an interrupt table; and in response to the interrupt number being found in the interrupt table, saving an address of a next instruction of the instrumented program after the interrupt instruction as a return address, determining a destination address, in an interrupt destination table, of a beginning of an instrumentation handler program associated with the interrupt number and transferring control of the instrumented program to the instrumentation handler program at the destination address.

    EFFICIENT EXCEPTION HANDLING IN TRUSTED EXECUTION ENVIRONMENTS
    5.
    发明公开
    EFFICIENT EXCEPTION HANDLING IN TRUSTED EXECUTION ENVIRONMENTS 审中-公开

    公开(公告)号：US20230205869A1

    公开(公告)日：2023-06-29

    申请号：US17561412

    申请日：2021-12-23

    Applicant: Intel Corporation

    Inventor： Scott Constable ,  Bin Xing ,  Yuan Xiao ,  Krystof Zmudzinski ,  Mona Vij ,  Mark Shanahan ,  Francis McKeen ,  Ittai Anati

    IPC: G06F21/53 ,  G06F9/30

    CPC classification number: G06F21/53 ,  G06F9/30145 ,  G06F9/30105

    Abstract: Systems, methods, and apparatuses relating efficient exception handling in trusted execution environments are described. In an embodiment, a hardware processor includes a register, a decoder, and execution circuitry. The register has a field to be set to enable an architecturally protected execution environment at one of a plurality of contexts for code in an architecturally protected enclave in memory. The decoder is to decode an instruction having a format including a field for an opcode, the opcode to indicate that the execution circuitry is to perform a context change. The execution circuitry is to perform one or more operations corresponding to the instruction, the one or more operations including changing, within the architecturally protected enclave, from a first context to a second context.

    Cache set permutations based on Galois Field operations
    7.
    发明授权
    Cache set permutations based on Galois Field operations 有权

    公开(公告)号：US12019563B2

    公开(公告)日：2024-06-25

    申请号：US17032883

    申请日：2020-09-25

    Applicant: Intel Corporation

    Inventor： Scott Constable ,  Thomas Unterluggauer

    IPC: G06F12/14 ,  G06F12/084 ,  G06F12/0864 ,  G06F12/0891

    CPC classification number: G06F12/1433 ,  G06F12/084 ,  G06F12/0864 ,  G06F12/0891

    Abstract: Systems, apparatuses and methods provide for technology that determines that first data associated with a first security domain is to be stored in a first permutated cache set, where the first permuted cache set is identified based on a permutation function that permutes at least one of a plurality of first cache indexes. The technology further determines that second data associated with a second security domain is to be stored in a second permutated cache set, where the second permuted cache set is identified based on the permutation function. The second permutated cache set may intersect the first permutated cache set at one data cache line to cause an eviction of first data associated with the first security domain from the one data cache line and bypass eviction of data associated with the first security domain from at least one other data cache line of the first permuted cache set.

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