公开(公告)号：US09698108B1

公开(公告)日：2017-07-04

申请号：US14998096

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Xavier F. Brun ,  Shweta Agrawal ,  Hao Wu ,  Mohit Mamodia ,  Shengquan E. Ou ,  Hualiang Shi

IPC: H01L21/78 ,  H01L23/58 ,  H01L23/48 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/585 ,  H01L21/76885 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/481 ,  H01L23/5283 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Techniques and mechanisms to mitigate contamination of redistribution layer structures disposed on a back side of a semiconductor substrate. In an embodiment, a microelectronics device includes a substrate and integrated circuitry variously formed in or on a front side of the substrate, where vias extend from the integrated circuitry to a back side of the substrate. A redistribution layer disposed on the back side includes a ring structure and a plurality of raised structures each extending from a recess portion that is surrounded by the ring structure. The ring structure and the plurality of raised structures provide contact surfaces for improved adhesion of dicing tape to the back side. In another embodiment, the plurality of raised structures includes dummification comprising dummy structures that are each electrically decoupled from any via extending through the substrate.