公开(公告)号：US20200006180A1

公开(公告)日：2020-01-02

申请号：US16024697

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Andrew BROWN ,  Ji Yong PARK ,  Siddharth ALUR ,  Cheng XU ,  Amruthavalli ALUR

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/29

Abstract: Embodiments include an electronic package and methods of forming an electronic package. In an embodiment, the electronic package comprises a substrate, and a plurality of conductive features formed over the substrate. In an embodiment, a bilayer build-up layer is formed over the plurality of conductive features. In an embodiment, the bilayer build-up layer comprises a first dielectric layer and a second dielectric layer. In an embodiment, a surface of the first dielectric layer comprises depressions. In an embodiment, the second dielectric layer is disposed in the depressions of the surface of the first dielectric layer.

公开(公告)号：US20240070366A1

公开(公告)日：2024-02-29

申请号：US17895107

申请日：2022-08-25

Applicant: Intel Corporation

Inventor： Nicholas HAEHN ,  Raquel DE SOUZA BORGES FERREIRA ,  Siddharth ALUR ,  Prakaram JOSHI ,  Dhanya ATHREYA ,  Yidnekachew MEKONNEN ,  Ali HARIRI ,  Andrea NICOLAS ,  Sri Chaitra Jyotsna CHAVALI ,  Kemal AYGUN

IPC: G06F30/392 ,  H01L23/498

CPC classification number: G06F30/392 ,  H01L23/49838 ,  G06F2119/22 ,  H01L23/49822

Abstract: A package substrate stack modeler includes a manufacturing modeler, configured to generate a model of a real package substrate stack based on an ideal design of the package substrate stack; a signal integrity model, configured to determine a signal integrity of a metal trace of the real package substrate stack; and a yield model, configured to determine a yield of the real package substrate stack; wherein the metal trace comprises a first value of a trace variable; further comprising a processor, configured to select a second value of the trace variable of the metal trace based on the determined signal integrity of the metal trace or the determined yield of the package substrate stack model.

公开(公告)号：US20190393606A1

公开(公告)日：2019-12-26

申请号：US16017093

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Sri Chaitra CHAVALI ,  Siddharth ALUR ,  Sheng LI

IPC: H01Q9/04 ,  H01Q5/35 ,  H01L23/66

Abstract: Embodiments include antennas, methods of forming antennas, and a semiconductor package. An antenna includes a feed port disposed in a substrate, and the feed port having a first patch and a second patch. The first patch is disposed on a top surface of substrate, and the second patch is disposed on a bottom surface of substrate. The antenna includes a photoimageable dielectric (PID) disposed on the bottom surface of substrate, where PID surrounds the second patch. The antenna includes a third patch disposed on PID, where the third patch is below the second patch. The antenna includes a cavity disposed between the second and third patches, where the cavity is enclosed by PID and third patch. An additional antenna includes a patch disposed on a first substrate, and a feed port disposed in a second substrate. This antenna includes a composite layer disposed between the first and second substrates.