公开(公告)号：US20250113503A1

公开(公告)日：2025-04-03

申请号：US18478840

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Nicolas Butzen ,  Harish K. Krishnamurthy ,  Khondker Ahmed ,  Nachiket Desai ,  Su Hwan Kim ,  Krishnan Ravichandran ,  Kaladhar Radhakrishnan ,  Jonathan Douglas

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: Embodiments herein relate to techniques to integrate a capacitive voltage regulator in an integrated circuit (IC) package. The voltage regulator may provide a power supply to one or more load domains in the IC package. The transistors of the voltage regulator may be included on the same die as one or more of the load domains, another die, and/or an interposer of the IC package. The capacitors may be included in the same die as the transistors, in the interposer, in a package layer (e.g., package core), and/or in the same die as one or more of the load domains. Accordingly, the voltage regulator can be integrated close to the relevant load domains, delivering power with short current paths and thereby providing reduced input impedance, output impedance, and associated losses compared with prior techniques. Other embodiments may be described and claimed.

公开(公告)号：US20250105144A1

公开(公告)日：2025-03-27

申请号：US18474160

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Su Hwan Kim ,  Harish K. Krishnamurthy ,  Nachiket Desai ,  Khondker Ahmed ,  Nicolas Butzen ,  Krishnan Ravichandran ,  Kaladhar Radhakrishnan

IPC: H01L23/522 ,  H01L23/498 ,  H01L25/065 ,  H02M3/335

Abstract: Embodiments herein relate to a voltage regular (VR) formed from die stacked on a package base layer. The die can include a load die stacked on a VR die, with an intermediate layer between the two dies. The VR can include an inductor or transformer as a charge transfer component formed between the dies. For example, the inductor or transformer windings can wind around the intermediate layer and include portions of top metal layers of the VR and load die, where the load die is inverted in the stack. The intermediate layer can be magnetic or non-magnetic for an inductor, or magnetic for a transformer. The VR can optionally be divided among two dies. The VR die may have a gallium nitride substrate to handle a higher input voltage, while the load die comprises a silicon substrate.

公开(公告)号：US20250103075A1

公开(公告)日：2025-03-27

申请号：US18474156

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Khondker Ahmed ,  Nicolas Butzen ,  Nachiket Desai ,  Su Hwan Kim ,  Harish K. Krishnamurthy ,  Krishnan Ravichandran ,  Kaladhar Radhakrishnan ,  Jonathan Douglas

IPC: G05F1/56

Abstract: Embodiments herein relate to a stacked semiconductor structure which includes a first voltage regulator (VR), external to a package, for supplying current to a compute die in the package. When the required current exceeds a threshold, an additional current source is activated. The additional current source can include a second VR, also external to the package, for supplying current to an integrated voltage regulator (IVR) in the package. The IVR performs voltage down conversion and current multiplication to output a portion of the required current above the threshold, while the output of the first VR is capped at the threshold.

公开(公告)号：US20250103074A1

公开(公告)日：2025-03-27

申请号：US18474147

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Harish K. Krishnamurthy ,  Nicolas Butzen ,  Khondker Ahmed ,  Nachiket Desai ,  Su Hwan Kim ,  Krishnan Ravichandran ,  Kaladhar Radhakrishnan ,  Jonathan Douglas

IPC: G05F1/56

Abstract: Embodiments herein relate to a voltage regular (VR) formed from dies stacked on a package base layer. The VR can include a first part on a first die and a second part on a second die, where the different parts are selected based on characteristics of the respective die such as their voltage domains or technologies. In a capacitor-based VR, an input capacitor and switches subject to a relatively high input voltage can be provided in the first die, while a flying capacitor, output capacitor and switches subject to a relatively low output voltage can be provided in the second die. In an inductor-based VR, an inductor and one or more switches subject to a relatively high input voltage can be provided in the first die, while an output capacitor subject to a relatively low output voltage can be provided in the second die.

公开(公告)号：US20240386937A1

公开(公告)日：2024-11-21

申请号：US18318659

申请日：2023-05-16

Applicant: Intel Corporation

Inventor： Su Hwan Kim ,  Chi-Hsiang Huang ,  Harish K. Krishnamurthy

IPC: G11C11/4074 ,  H02M1/00 ,  H02M3/07 ,  H02M3/158

Abstract: Various embodiments herein provide a switched capacitor voltage converter with a subset of one or more phases that selectively provide a decoupling capacitance. The voltage converter may include multiple phases coupled in parallel between an input terminal and an output terminal. The individual phases may include a capacitor and a set of switches. A first subset of one or more of the phases may operate in a switching mode in which the respective set of switches open and close to generate an output voltage at the output terminal based on an input voltage at the input terminal. The voltage converter may further include a second subset of one or more phases that are selectively operable in the switching mode or in a decoupling mode. In the decoupling mode, the switches of the respective phase may maintain the capacitor coupled between the output terminal and ground. Other embodiments may be described and claimed.