公开(公告)号：US20220138895A1

公开(公告)日：2022-05-05

申请号：US17430041

申请日：2020-03-14

Applicant: Intel Corporation

Inventor： Vasanth Raganathan ,  Abhishek R. Appu ,  Ben Ashbaugh ,  Peter Doyle ,  Brandon Fliflet ,  Arthur Hunter ,  Brent Insko ,  Scott Janus ,  Altug Koker ,  Aditya Navale ,  Joydeep Ray ,  Kamal Sinha ,  Lakshminarayanan Striramassarma ,  Prasoonkumar Surti ,  James Valerio

IPC: G06T1/60 ,  G06T1/20 ,  G06F9/50

Abstract: Embodiments are generally directed to compute optimization in graphics processing. An embodiment of an apparatus includes one or more processors including a multi-tile graphics processing unit (GPU) to process data, the multi-tile GPU including multiple processor tiles; and a memory for storage of data for processing, wherein the apparatus is to receive compute work for processing by the GPU, partition the compute work into multiple work units, assign each of multiple work units to one of the processor tiles, and process the compute work using the processor tiles assigned to the work units.