公开(公告)号：US10970808B2

公开(公告)日：2021-04-06

申请号：US16449545

申请日：2019-06-24

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Subramaniam Maiyuran ,  Varghese George ,  Vivek Kumar Ilanchelian

IPC: G06T1/60 ,  G06F9/54 ,  G06T1/20

Abstract: A general-purpose graphics processor comprising a first set of compute units, a second set of compute units, and a memory coupled with the first set of compute units and the second set of compute units is described. The memory is configured to merge a first read request to an address block of the memory with a second read request to the address block of the memory to reduce a number of memory accesses to a memory bank associated with the address block. The graphics processor can also include a memory arbiter that can multicast merged reads to the compute units associated with the merged reads.