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公开(公告)号：US09525626B2
公开(公告)日：2016-12-20
申请号：US14816042
申请日：2015-08-02
Applicant: Intel Corporation
Inventor： Kay Keat Khoo , Vui Yong Liew , Hai Ming Khor
IPC: H04L12/773 , H04L12/64 , G06F13/38 , H04L12/933
CPC classification number: H04L45/60 , G06F13/38 , H04L12/6418 , H04L49/109
Abstract: Methods and apparatus for managing sideband routers in an On-Die System Fabric (OSF) are described. In one embodiment, a sideband OSF router is configurable during runtime based, at least in part, on information stored in a table accessible by an agent coupled to the sideband OSF router. Other embodiments are also disclosed.
Abstract translation: 描述了在片上系统架构（OSF）中管理边带路由器的方法和装置。 在一个实施例中，边缘OSF路由器可以在运行时至少部分地基于存储在由与边带OSF路由器耦合的代理可访问的表中的信息来配置。 还公开了其他实施例。
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公开(公告)号：US20210389371A1
公开(公告)日：2021-12-16
申请号：US17461364
申请日：2021-08-30
Applicant: Intel Corporation
Inventor： Vui Yong Liew , Zhenyu Zhu , Mikal C. Hunsaker , Wai Mun Ng
IPC: G01R31/317 , G01R31/3185 , G01R31/3193 , G06F13/16 , G06F13/42
Abstract: An apparatus comprises a first semiconductor chip comprising a first communication controller to receive first debug data from a second semiconductor chip; a memory to store the first debug data from the second semiconductor chip and second debug data of the first semiconductor chip; and a second communication controller to transmit the first debug data from the second semiconductor chip and the second debug data of the first semiconductor chip to an output port of the first semiconductor chip.
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公开(公告)号：US11138316B2
公开(公告)日：2021-10-05
申请号：US16457571
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： Vui Yong Liew
Abstract: An apparatus of a computing system, a computer-readable medium, a method and a system. The apparatus comprises an input/output interface and one or more processors connected to the input/output interface and adapted to perform a first reading of first fuse data stored in a fuse array storage circuitry to result in read first fuse data, and receive the read first fuse data from the fuse array storage circuitry through the input/output interface; after a random time-delay, perform a second reading of second fuse data stored in the fuse array storage circuitry to result in read second fuse data, and receive the read second fuse data from the fuse array storage circuitry through the input/output interface; and compare the read first fuse data with the read second fuse data, and if there is no match, halt a boot-up of the computing system.
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公开(公告)号：US09489028B2
公开(公告)日：2016-11-08
申请号：US13631870
申请日：2012-09-29
Applicant: Intel Corporation
Inventor： Hai Ming Khor , Kay Keat Khoo , Vui Yong Liew , Bhushan Vaidya
CPC classification number: G06F1/3206 , G06F1/3287 , G06F15/7825 , Y02D10/171 , Y02D50/20
Abstract: Methods and apparatus for managing sideband segments in an On-Die System Fabric (OSF) are described. In one embodiment, a sideband OSF includes a plurality of segments that may be reset or powered down independently after power management logic determines that in progress messages have been handled and future messages to the segment being reset or powered down will be blocked. Other embodiments are also disclosed.
Abstract translation: 描述了在片上系统架构（OSF）中管理边带段的方法和装置。 在一个实施例中，边带OSF包括多个段，其在电源管理逻辑确定正在进行的消息已被处理之后可以被独立地复位或掉电，并且到该段的未来消息被复位或掉电将被阻止。 还公开了其他实施例。
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公开(公告)号：US10236076B2
公开(公告)日：2019-03-19
申请号：US15282574
申请日：2016-09-30
Applicant: Intel Corporation
Inventor： Wei Ming Lim , Madhu Rao , Alvin Shing Chye Goh , Kim Leong Lee , Terrence Huat Hin Tan , Vui Yong Liew , Yah Chen Chew
Abstract: Methods and apparatus for predictable protocol aware testing on a memory interface are are shown. An apparatus to support a protocol aware testing on a memory interface may include a digital controller to receive a plurality of read request commands from a unit under test. The digital controller further to hold the plurality of read request commands while a hold signal has a first value, and to sequentially release individual read request commands of the plurality of read request commands while to the hold signal has a second value. The digital controller further to provide input/output (I/O) commands to an output based on a particular released read request command of the plurality of read request commands. Timing of provision of the I/O commands is deterministic based on a transition of the hold signal from the first value to the second value.
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Patent Agency Ranking
公开(公告)号：US20150341260A1
公开(公告)日：2015-11-26
申请号：US14816042
申请日：2015-08-02
Applicant: Intel Corporation
Inventor： Kay Keat Khoo , Vui Yong Liew , Hai Ming Khor
IPC: H04L12/773 , H04L12/933
CPC classification number: H04L45/60 , G06F13/38 , H04L12/6418 , H04L49/109
Abstract: Methods and apparatus for managing sideband routers in an On-Die System Fabric (OSF) are described. In one embodiment, a sideband OSF router is configurable during runtime based, at least in part, on information stored in a table accessible by an agent coupled to the sideband OSF router. Other embodiments are also disclosed.
Abstract translation: 描述了在片上系统架构（OSF）中管理边带路由器的方法和装置。 在一个实施例中，边带OSF路由器可以在运行时至少部分地基于存储在由与边带OSF路由器耦合的代理可访问的表中的信息来配置。 还公开了其他实施例。
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公开(公告)号：US20190325141A1
公开(公告)日：2019-10-24
申请号：US16457571
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： Vui Yong Liew
Abstract: An apparatus of a computing system, a computer-readable medium, a method and a system. The apparatus comprises an input/output interface and one or more processors connected to the input/output interface and adapted to perform a first reading of first fuse data stored in a fuse array storage circuitry to result in read first fuse data, and receive the read first fuse data from the fuse array storage circuitry through the input/output interface; after a random time-delay, perform a second reading of second fuse data stored in the fuse array storage circuitry to result in read second fuse data, and receive the read second fuse data from the fuse array storage circuitry through the input/output interface; and compare the read first fuse data with the read second fuse data, and if there is no match, halt a boot-up of the computing system.
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公开(公告)号：US20180096737A1
公开(公告)日：2018-04-05
申请号：US15282574
申请日：2016-09-30
Applicant: Intel Corporation
Inventor： Wei Ming Lim , Madhu Rao , Alvin Shing Chye Goh , Kim Leong Lee , Terrence Huat Hin Tan , Vui Yong Liew , Yah Chen Chew
CPC classification number: G11C29/56004 , G06F1/10 , G11C29/56012 , G11C2029/5602
Abstract: Methods and apparatus for predictable protocol aware testing on a memory interface are are shown. An apparatus to support a protocol aware testing on a memory interface may include a digital controller to receive a plurality of read request commands from a unit under test. The digital controller further to hold the plurality of read request commands while a hold signal has a first value, and to sequentially release individual read request commands of the plurality of read request commands while to the hold signal has a second value. The digital controller further to provide input/output (I/O) commands to an output based on a particular released read request command of the plurality of read request commands. Timing of provision of the I/O commands is deterministic based on a transition of the hold signal from the first value to the second value.
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公开(公告)号：US09100348B2
公开(公告)日：2015-08-04
申请号：US13631871
申请日：2012-09-29
Applicant: Intel Corporation
Inventor： Kay Keat Khoo , Vui Yong Liew , Hai Ming Khor
IPC: H04L12/773 , H04L12/64 , G06F13/38
CPC classification number: H04L45/60 , G06F13/38 , H04L12/6418 , H04L49/109
Abstract: Methods and apparatus for managing sideband routers in an On-Die System Fabric (OSF) are described. In one embodiment, a sideband OSF router is configurable during runtime based, at least in part, on information stored in a table accessible by an agent coupled to the sideband OSF router. Other embodiments are also disclosed.
Abstract translation: 描述了在片上系统架构（OSF）中管理边带路由器的方法和装置。 在一个实施例中，边带OSF路由器可以在运行时至少部分地基于存储在由与边带OSF路由器耦合的代理可访问的表中的信息来配置。 还公开了其他实施例。
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公开(公告)号：US11933843B2
公开(公告)日：2024-03-19
申请号：US17377264
申请日：2021-07-15
Applicant: Intel Corporation
Inventor： Keith A. Jones , Wai Mun Ng , Thomas A. Lyda , Subinlal Pk , Sankaran Menon , Vui Yong Liew , Kristan K. Wiseley
IPC: G01R31/317 , G01R31/3183 , G01R31/3185
CPC classification number: G01R31/31721 , G01R31/31705 , G01R31/318314 , G01R31/318533
Abstract: An Automated Dynamic low voltage monitoring (LVM) based Low-Power (ADLLP) debug capability for a system-on-chip (SoC) as well as the open/closed-chassis platform for faster TTM (Time to Market) of the final platform or system. ADLLP Debug is achieved by detection of the probe connection between a target system (e.g., SoC) and debug host system. A user can dynamically override the power, clocks and LVM for intellectual property (IP) blocks not part of the debug trace by instructing a Power Management Controller (PMC) via the Inter Processor Communication (IPC) mailbox (or any other suitable mailbox driver) to set the registers in a Target Firmware (TFW) based on the probe and debug use-case.
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