公开(公告)号：US10445118B2

公开(公告)日：2019-10-15

申请号：US15713301

申请日：2017-09-22

Applicant: Intel Corporation

Inventor： Xiangyang Guo ,  Simonjit Dutta ,  Han Lee ,  Yipeng Wang

IPC: G06F9/44 ,  G06F9/455 ,  G06F8/41

Abstract: Methods, apparatus, systems, and articles of manufacture to facilitate field-programmable gate array support during runtime execution of computer readable instructions are disclosed herein. An example apparatus includes a compiler to, prior to runtime, compile a block of code written as high level source code into a first hardware bitstream kernel and a second hardware bitstream kernel; a kernel selector to select the first hardware bitstream kernel based on an attribute to be dispatched during runtime; a dispatcher to dispatch the first hardware bitstream kernel to a field programmable gate array (FPGA) during runtime; and the kernel selector to, when an FPGA attribute does not satisfy a threshold during runtime, adjust the selection of the first hardware bitstream kernel to the second hardware bitstream kernel to be dispatched during runtime.

公开(公告)号：US10789176B2

公开(公告)日：2020-09-29

申请号：US16059147

申请日：2018-08-09

Applicant: Intel Corporation

Inventor： Ren Wang ,  Yipeng Wang ,  Tsung-Yuan Tai ,  Cristian Florin Dumitrescu ,  Xiangyang Guo

IPC: G06F12/123 ,  G06F12/126 ,  G06F12/128 ,  G06F12/0864 ,  G06F12/0891 ,  G06F9/30 ,  G06F12/0871

Abstract: Technologies for least recently used (LRU) cache replacement include a computing device with a processor with vector instruction support. The computing device retrieves a bucket of an associative cache from memory that includes multiple entries arranged from front to back. The bucket may be a 256-bit array including eight 32-bit entries. For lookups, a matching entry is located at a position in the bucket. The computing device executes a vector permutation processor instruction that moves the matching entry to the front of the bucket while preserving the order of other entries of the bucket. For insertion, an inserted entry is written at the back of the bucket. The computing device executes a vector permutation processor instruction that moves the inserted entry to the front of the bucket while preserving the order of other entries. The permuted bucket is stored to the memory. Other embodiments are described and claimed.

公开(公告)号：US20190042395A1

公开(公告)日：2019-02-07

申请号：US16145399

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Li Tian ,  Varun K. Venkatesan ,  Richard Kozlak ,  Priyanka Hegde ,  Vincent Zimmer ,  Rodolfo Esteves Jaramillo ,  Xiangyang Guo

IPC: G06F11/36 ,  G06F11/34 ,  G06F8/41 ,  G06F8/30

Abstract: Systems, apparatuses and methods may provide for technology that may profile a first low-level language code to identify a first latency of a first portion of the first low-level language code. The technology may map the first portion to a source portion of a source code based on an identification that the first portion is a low-level language code representation of the source portion. The source code may be a high-level language code. The technology may associate the first latency with the source portion based on the mapping.

公开(公告)号：US11409506B2

公开(公告)日：2022-08-09

申请号：US16142401

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Yipeng Wang ,  Ren Wang ,  Tsung-Yuan C. Tai ,  Jr-Shian Tsai ,  Xiangyang Guo

IPC: G06F9/44 ,  G06F9/445 ,  G06F11/36 ,  G06F8/41 ,  G06F9/455 ,  G06F8/30

Abstract: Examples may include a method of compiling a declarative language program for a virtual switch. The method includes parsing the declarative language program, the program defining a plurality of match-action tables (MATs), translating the plurality of MATs into intermediate code, and parsing a core identifier (ID) assigned to each one of the plurality of MATs. When the core IDs of the plurality of MATs are the same, the method includes connecting intermediate code of the plurality of MATs using function calls, and translating the intermediate code of the plurality of MATs into machine code to be executed by a core identified by the core IDs.

公开(公告)号：US20190042471A1

公开(公告)日：2019-02-07

申请号：US16059147

申请日：2018-08-09

Applicant: Intel Corporation

Inventor： Ren Wang ,  Yipeng Wang ,  Tsung-Yuan Tai ,  Cristian Florin Dumitrescu ,  Xiangyang Guo

IPC: G06F12/123 ,  G06F12/128 ,  G06F12/126 ,  G06F12/0891 ,  G06F12/0871 ,  G06F12/0864 ,  G06F9/30

Abstract: Technologies for least recently used (LRU) cache replacement include a computing device with a processor with vector instruction support. The computing device retrieves a bucket of an associative cache from memory that includes multiple entries arranged from front to back. The bucket may be a 256-bit array including eight 32-bit entries. For lookups, a matching entry is located at a position in the bucket. The computing device executes a vector permutation processor instruction that moves the matching entry to the front of the bucket while preserving the order of other entries of the bucket. For insertion, an inserted entry is written at the back of the bucket. The computing device executes a vector permutation processor instruction that moves the inserted entry to the front of the bucket while preserving the order of other entries. The permuted bucket is stored to the memory. Other embodiments are described and claimed.