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    Digital intensive hybrid ADC/filter for LNA-free adaptive radio front-ends
    2.
    发明授权
    Digital intensive hybrid ADC/filter for LNA-free adaptive radio front-ends 有权
    数字强度混合ADC /滤波器，用于无LNA自适应无线电前端

    公开(公告)号：US09584164B1

    公开(公告)日：2017-02-28

    申请号：US15049616

    申请日：2016-02-22

    Applicant: Intel Corporation

    Inventor： Farhana Sheikh ,  Amy L. Whitcombe ,  Erkan Alpman ,  Yanjie Wang ,  Shreyas Sen

    IPC: H04B1/00 ,  H04B1/10 ,  H04L27/00

    CPC classification number: H04B1/0042 ,  H04B1/10 ,  H04L27/0002

    Abstract: A mixer-first receiver operates to generate filtering and analog-to-digital conversion concurrently and adaptively, while removing an LNA before a mixer to enable integration with digital baseband circuits. A plurality of switching capacitor arrays are integrated with a hybrid analog-to-digital filtering component. Switching capacitor arrays of the plurality of switching capacitor arrays can be selectively modified to perform both the filtering operation and the conversion operation together. The same switch capacitors of a switching capacitor array can be utilized in one phase of a clock cycle for the filtering and in another phase of the clock cycle for the conversion.

    Abstract translation: 混频器第一接收机用于同时和自适应地产生滤波和模数转换，同时在混频器之前去除LNA以实现与数字基带电路的集成。 多个开关电容器阵列与混合模数转换组件集成。 可以选择性地修改多个开关电容器阵列的开关电容器阵列以一起执行滤波操作和转换操作。 开关电容器阵列的相同开关电容器可以在用于滤波的时钟周期的一个阶段中用于转换的时钟周期的另一个阶段。

    Phase modulation systems and methods
    3.
    发明授权
    Phase modulation systems and methods 有权

    公开(公告)号：US10594309B2

    公开(公告)日：2020-03-17

    申请号：US16025148

    申请日：2018-07-02

    Applicant: Intel Corporation

    Inventor： Abhishek Agrawal ,  Stefano Pellerano ,  Yanjie Wang ,  Peter Sagazio

    IPC: H03K7/06 ,  H04L27/20

    Abstract: In a phase modulation method enable signals may be sequentially generating based on a clock signal to generate a sequence of enable signals, and a signal is delayed by delay values generated from delay cells based on the sequence of enable signals and digital bit values. A phase modulator may include a first delay circuit configured to: delay a clock signal based on a first delay value to generate a first delayed clock signal, and delay a carrier signal based on the first delayed clock signal to generate a first delayed carrier signal; and a second delay circuit configured to: delay the first delayed clock signal based on a second delay value to generate a second delayed clock signal, and delay the first delayed carrier signal based on the second delayed clock signal to generate a second delayed carrier signal.

    PHASE MODULATION SYSTEMS AND METHODS
    7.
    发明申请
    PHASE MODULATION SYSTEMS AND METHODS 审中-公开

    公开(公告)号：US20200007116A1

    公开(公告)日：2020-01-02

    申请号：US16025148

    申请日：2018-07-02

    Applicant: Intel Corporation

    Inventor： Abhishek Agrawal ,  Stefano Pellerano ,  Yanjie Wang ,  Peter Sagazio

    IPC: H03K7/06 ,  H04L27/20

    Abstract: In a phase modulation method enable signals may be sequentially generating based on a clock signal to generate a sequence of enable signals, and a signal is delayed by delay values generated from delay cells based on the sequence of enable signals and digital bit values. A phase modulator may include a first delay circuit configured to: delay a clock signal based on a first delay value to generate a first delayed clock signal, and delay a carrier signal based on the first delayed clock signal to generate a first delayed carrier signal; and a second delay circuit configured to: delay the first delayed clock signal based on a second delay value to generate a second delayed clock signal, and delay the first delayed carrier signal based on the second delayed clock signal to generate a second delayed carrier signal.

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