公开(公告)号：US20160179666A1

公开(公告)日：2016-06-23

申请号：US14573811

申请日：2014-12-17

Applicant: Intel Corporation

Inventor： Daniel Greenspan ,  Yoav Lossin ,  Blaise Fanning ,  Nagi Aboulenein ,  Marc Torrant

IPC: G06F12/08

CPC classification number: G06F12/082 ,  G06F11/34 ,  G06F12/0607 ,  G06F12/0864 ,  G06F12/0895 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/1028 ,  G06F2212/1044 ,  G06F2212/608 ,  Y02D10/13

Abstract: In an embodiment, a processor includes at least one core, a cache memory, and a cache controller. Responsive to a request to store an address of a data entry into the cache memory, the cache controller is to determine whether an initial cache set of the cache memory and corresponding to the address has available capacity to store the address. Responsive to unavailability of capacity in the initial cache set, the cache controller is to generate a first alternate address associated with the data entry and to determine whether a first cache set corresponding to the first alternate address has available capacity to store the alternate address and if so to store the first alternate address in the first cache set. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括至少一个核心，高速缓存存储器和高速缓存控制器。 响应于将数据条目的地址存储到高速缓冲存储器中的请求，高速缓存控制器将确定高速缓冲存储器的初始高速缓存集是否具有可用于存储该地址的容量。 响应于初始高速缓存集中的容量不可用，高速缓存控制器将生成与数据条目相关联的第一备用地址，并且确定对应于第一备用地址的第一高速缓存集是否具有存储备用地址的可用容量，以及如果 所以要将第一个备用地址存储在第一个缓存集中。 描述和要求保护其他实施例。

公开(公告)号：US10657070B2

公开(公告)日：2020-05-19

申请号：US16105434

申请日：2018-08-20

Applicant: Intel Corporation

Inventor： Daniel Greenspan ,  Blaise Fanning ,  Yoav Lossin ,  Asaf Rubinstein

IPC: G06F12/123 ,  G06F12/0891 ,  G06F12/0897

Abstract: A method and apparatus are described for a shared LRU policy between cache levels. For example, one embodiment comprises: a level N cache to store a first plurality of entries; a level N+1 cache to store a second plurality of entries; the level N+1 cache to initially be provided with responsibility for implementing a least recently used (LRU) eviction policy for a first entry until receipt of a request for the first entry from the level N cache at which time the entry is copied from the level N+1 cache to the level N cache, the level N cache to then be provided with responsibility for implementing the LRU policy until the first entry is evicted from the level N cache, wherein upon being notified that the first entry has been evicted from the level N cache, the level N+1 cache to resume responsibility for implementing the LRU eviction policy.

公开(公告)号：US09767042B2

公开(公告)日：2017-09-19

申请号：US14631257

申请日：2015-02-25

Applicant: Intel Corporation

Inventor： Daniel Greenspan ,  Yoav Lossin

IPC: G06F12/00 ,  G06F12/122 ,  G06F12/128 ,  G06F1/32

CPC classification number: G06F12/122 ,  G06F1/3203 ,  G06F1/3275 ,  G06F12/128 ,  G06F2212/1028 ,  G06F2212/6032 ,  Y02D10/13 ,  Y02D10/14

Abstract: Systems and methods for improving write-back cache performance by utilizing scrubbed state indicators associated with the cache entries. The example system may comprise: a cache comprising a plurality of cache entries; a processing core, coupled to the cache; and a cache controller configured to maintain a plurality of indicators corresponding to a plurality of cache entries, wherein each indicator of the plurality of indicators indicates whether a corresponding cache entry has been scrubbed by synchronizing the cache entry with a next level memory after the cache entry has been modified.

公开(公告)号：US20160335187A1

公开(公告)日：2016-11-17

申请号：US14709323

申请日：2015-05-11

Applicant: Intel Corporation

Inventor： Daniel Greenspan ,  Anant V. Nori ,  Supratik Majumder ,  Yoav Lossin ,  Asaf Rubinstein

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0864 ,  G06F12/0851 ,  G06F12/123 ,  G06F12/128 ,  G06F2212/1024 ,  G06F2212/6032 ,  Y02D10/13

Abstract: Integrated circuits are provided which create page locality in cache controllers that allocate entries to set-associative cache, which includes data storage for a plurality of Sets of Ways. A plurality of cache controllers may be interleaved with a processor and device(s), and allocate to any pages in the cache. A cache controller may select a Way from a Set to which to allocate new entries in the set-associative cache and bias selection of the Way according to a plurality of upper address bits (or other function). These bits may be identical at the cache controller during sequential memory transactions. A processor may determine the bias centrally, and inform the cache controllers of the selected Set and Way. Other functions, algorithms or approaches may be chosen to influence bias of Way selection, such as based on analysis of metadata belonging to cache controllers used for making Way allocation selections.

Abstract translation: 提供集成电路，其在高速缓存控制器中创建页面位置，其将条目分配给设置关联高速缓存，其包括用于多个方式集合的数据存储。 多个高速缓存控制器可以与处理器和设备进行交织，并且分配给高速缓存中的任何页面。 高速缓存控制器可以根据多个高位地址位（或其他功能），从集合中选择一个路径，该集合将在集合相关高速缓存中分配新条目，并根据多个高位地址位（或其他功能）偏移选择道。 这些位在顺序存储器事务期间在高速缓存控制器上可以是相同的。 处理器可以集中地确定偏差，并且向高速缓存控制器通知所选择的集合和方式。 可以选择其他功能，算法或方法来影响Way选择的偏向，例如基于属于用于进行Way分配选择的高速缓存控制器的元数据的分析。

公开(公告)号：US20170357599A1

公开(公告)日：2017-12-14

申请号：US15670542

申请日：2017-08-07

Applicant: Intel Corporation

Inventor： Daniel Greenspan ,  Yoav Lossin

IPC: G06F12/122 ,  G06F12/128 ,  G06F1/32

CPC classification number: G06F12/122 ,  G06F1/3203 ,  G06F1/3275 ,  G06F12/128 ,  G06F2212/1028 ,  G06F2212/6032 ,  Y02D10/13 ,  Y02D10/14

Abstract: Systems and methods for improving write-back cache performance by utilizing scrubbed state indicators associated with the cache entries. The example system may comprise: a cache comprising a plurality of cache entries; a processing core, coupled to the cache; and a cache controller configured to maintain a plurality of indicators corresponding to a plurality of cache entries, wherein each indicator of the plurality of indicators indicates whether a corresponding cache entry has been scrubbed by synchronizing the cache entry with a next level memory after the cache entry has been modified.

公开(公告)号：US20160246734A1

公开(公告)日：2016-08-25

申请号：US14631257

申请日：2015-02-25

Applicant: Intel Corporation

Inventor： Daniel Greenspan ,  Yoav Lossin

IPC: G06F12/12 ,  G06F1/32

CPC classification number: G06F12/122 ,  G06F1/3203 ,  G06F1/3275 ,  G06F12/128 ,  G06F2212/1028 ,  G06F2212/6032 ,  Y02D10/13 ,  Y02D10/14

Abstract: Systems and methods for improving write-back cache performance by utilizing scrubbed state indicators associated with the cache entries. The example system may comprise: a cache comprising a plurality of cache entries; a processing core, coupled to the cache; and a cache controller configured to maintain a plurality of indicators corresponding to a plurality of cache entries, wherein each indicator of the plurality of indicators indicates whether a corresponding cache entry has been scrubbed by synchronizing the cache entry with a next level memory after the cache entry has been modified.

Abstract translation: 通过利用与缓存条目关联的擦除状态指示来提高回写缓存性能的系统和方法。 示例系统可以包括：包括多个高速缓存条目的高速缓存; 处理核心，耦合到缓存; 以及缓存控制器，被配置为维护对应于多个高速缓存条目的多个指示符，其中所述多个指示符中的每个指示符指示在所述高速缓存条目之后通过将所述高速缓存条目与下一级存储器同步来对相应的高速缓存条目是否进行了擦除 已被修改。

公开(公告)号：US09846648B2

公开(公告)日：2017-12-19

申请号：US14709323

申请日：2015-05-11

Applicant: Intel Corporation

Inventor： Daniel Greenspan ,  Anant V. Nori ,  Supratik Majumder ,  Yoav Lossin ,  Asaf Rubinstein

IPC: G06F12/0864 ,  G06F12/0846 ,  G06F12/128 ,  G06F12/123

CPC classification number: G06F12/0864 ,  G06F12/0851 ,  G06F12/123 ,  G06F12/128 ,  G06F2212/1024 ,  G06F2212/6032 ,  Y02D10/13

Abstract: Integrated circuits are provided which create page locality in cache controllers that allocate entries to set-associative cache, which includes data storage for a plurality of Sets of Ways. A plurality of cache controllers may be interleaved with a processor and device(s), and allocate to any pages in the cache. A cache controller may select a Way from a Set to which to allocate new entries in the set-associative cache and bias selection of the Way according to a plurality of upper address bits (or other function). These bits may be identical at the cache controller during sequential memory transactions. A processor may determine the bias centrally, and inform the cache controllers of the selected Set and Way. Other functions, algorithms or approaches may be chosen to influence bias of Way selection, such as based on analysis of metadata belonging to cache controllers used for making Way allocation selections.

公开(公告)号：US09514047B2

公开(公告)日：2016-12-06

申请号：US14573811

申请日：2014-12-17

Applicant: Intel Corporation

Inventor： Daniel Greenspan ,  Yoav Lossin ,  Blaise Fanning ,  Nagi Aboulenein ,  Marc Torrant

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/082 ,  G06F11/34 ,  G06F12/0607 ,  G06F12/0864 ,  G06F12/0895 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/1028 ,  G06F2212/1044 ,  G06F2212/608 ,  Y02D10/13

Abstract: In an embodiment, a processor includes at least one core, a cache memory, and a cache controller. Responsive to a request to store an address of a data entry into the cache memory, the cache controller is to determine whether an initial cache set of the cache memory and corresponding to the address has available capacity to store the address. Responsive to unavailability of capacity in the initial cache set, the cache controller is to generate a first alternate address associated with the data entry and to determine whether a first cache set corresponding to the first alternate address has available capacity to store the alternate address and if so to store the first alternate address in the first cache set. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括至少一个核心，高速缓存存储器和高速缓存控制器。 响应于将数据条目的地址存储到高速缓冲存储器中的请求，高速缓存控制器将确定高速缓冲存储器的初始高速缓存集是否具有可用于存储该地址的容量。 响应于初始高速缓存集中的容量不可用，高速缓存控制器将生成与数据条目相关联的第一备用地址，并且确定对应于第一备用地址的第一高速缓存集是否具有存储备用地址的可用容量，以及如果 所以要将第一个备用地址存储在第一个缓存集中。 描述和要求保护其他实施例。

公开(公告)号：US10055360B2

公开(公告)日：2018-08-21

申请号：US14975752

申请日：2015-12-19

Applicant: Intel Corporation

Inventor： Daniel Greenspan ,  Blaise Fanning ,  Yoav Lossin ,  Asaf Rubinstein

IPC: G06F12/00 ,  G06F12/123 ,  G06F12/0891 ,  G06F12/0897

CPC classification number: G06F12/123 ,  G06F12/0891 ,  G06F12/0897 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/60 ,  Y02D10/13

Abstract: A method and apparatus are described for a shared LRU policy between cache levels. For example, one embodiment of the invention comprises: a level N cache to store a first plurality of entries; a level N+1 cache to store a second plurality of entries; the level N+1 cache to initially be provided with responsibility for implementing a least recently used (LRU) eviction policy for a first entry until receipt of a request for the first entry from the level N cache at which time the entry is copied from the level N+1 cache to the level N cache, the level N cache to then be provided with responsibility for implementing the LRU policy until the first entry is evicted from the level N cache, wherein upon being notified that the first entry has been evicted from the level N cache, the level N+1 cache to resume responsibility for implementing the LRU eviction policy with respect to the first entry.

公开(公告)号：US20180046579A1

公开(公告)日：2018-02-15

申请号：US15794172

申请日：2017-10-26

Applicant: Intel Corporation

Inventor： Daniel Greenspan ,  Anant V. Nori ,  Supratik Majumder ,  Yoav Lossin ,  Asaf Rubinstein

IPC: G06F12/0864 ,  G06F12/0846 ,  G06F12/128 ,  G06F12/123

CPC classification number: G06F12/0864 ,  G06F12/0851 ,  G06F12/123 ,  G06F12/128 ,  G06F2212/1024 ,  G06F2212/6032 ,  Y02D10/13

Abstract: A cache controller is to allocate memory within set-associative cache that includes a plurality of sets of ways. The cache controller is to request to assign an entry for a system address in the set-associative cache and execute a function to determine a set, from a series of sets within the plurality of sets of ways, to which to allocate the entry in the set-associative cache. The cache controller is further to identify an available number of ways in the set and identify a way that is available in response to execution of a way bias algorithm. The cache controller is also to determine whether the way is among the ways available within the set and select the way for allocation of the entry in response to the way being among the ways available within the set.