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公开(公告)号：US10511224B2
公开(公告)日：2019-12-17
申请号：US15944214
申请日：2018-04-03
Applicant: Intel Corporation
Inventor： Jaydeep Kulkarni , Yong Shim , Pascal A. Meinerzhagen , Muhammad M. Khellah
Abstract: Some embodiments include apparatus and methods using a charge pump coupled to a first supply power node and a second supply power node. The charge pump is arranged to transfer charge from the first supply power node to the second supply power node during a first time interval and to transfer charge from the second supply power node to the first supply power node during a second time interval.
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公开(公告)号：US20180226887A1
公开(公告)日：2018-08-09
申请号：US15944214
申请日：2018-04-03
Applicant: Intel Corporation
Inventor： Jaydeep Kulkarni , Yong Shim , Pascal A. Meinerzhagen , Muhammad M. Khellah
Abstract: Some embodiments include apparatus and methods using a charge pump coupled to a first supply power node and a second supply power node. The charge pump is arranged to transfer charge from the first supply power node to the second supply power node during a first time interval and to transfer charge from the second supply power node to the first supply power node during a second time interval.
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Patent Agency Ranking
公开(公告)号：US20170344090A1
公开(公告)日：2017-11-30
申请号：US15163494
申请日：2016-05-24
Applicant: Intel Corporation
Inventor： Jaydeep P. Kulkarni , Yong Shim , Pascal A. Meinerzhagen
CPC classification number: G06F1/324 , G06F1/3287 , G06F1/3296 , H02M3/07 , Y02D10/171 , Y02D10/172
Abstract: Described is an apparatus which comprises: a controllable power gate coupled to an ungated power supply node and a gated power supply node; and a charge-pump circuit operable to be turned on and off according to a logic, wherein the charge pump circuit is coupled in parallel to the controllable power gate and also coupled to the ungated power supply node and the gated power supply node.
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公开(公告)号：US11079830B2
公开(公告)日：2021-08-03
申请号：US15163494
申请日：2016-05-24
Applicant: Intel Corporation
Inventor： Jaydeep P. Kulkarni , Yong Shim , Pascal A. Meinerzhagen
IPC: H02M3/07 , G06F1/324 , G06F1/3296 , G06F1/3287
Abstract: Described is an apparatus which comprises: a controllable power gate coupled to an ungated power supply node and a gated power supply node; and a charge-pump circuit operable to be turned on and off according to a logic, wherein the charge pump circuit is coupled in parallel to the controllable power gate and also coupled to the ungated power supply node and the gated power supply node.
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公开(公告)号：US10014767B2
公开(公告)日：2018-07-03
申请号：US15081445
申请日：2016-03-25
Applicant: Intel Corporation
Inventor： Jaydeep Kulkarni , Yong Shim , Pascal A. Meinerzhagen , Muhammad M. Khellah
CPC classification number: H02M3/07 , H02M2001/0032 , H03K3/0315 , H03K5/19
Abstract: Some embodiments include apparatus and methods using a charge pump coupled to a first supply power node and a second supply power node. The charge pump is arranged to transfer charge from the first supply power node to the second supply power node during a first time interval and to transfer charge from the second supply power node to the first supply power node during a second time interval.
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公开(公告)号：US09755631B2
公开(公告)日：2017-09-05
申请号：US14951343
申请日：2015-11-24
Applicant: Intel Corporation
Inventor： Yong Shim , Jaydeep P. Kulkarni , Pascal A. Meinerzhagen , Muhammad M. Khellah
IPC: G05F1/10 , H03K17/081 , H03K17/14 , H03K3/037
CPC classification number: H03K17/08104 , H03K3/0377 , H03K17/145 , H03K19/0016
Abstract: Described is an apparatus which comprises: a power gate transistor coupled to an ungated power supply node and a gated power supply node, the power gate transistor having a gate terminal; a resistive device; a first transistor coupled in series with the resistive device together forming a pair, the first transistor also coupled to the gate terminal of the power gate transistor; a capacitive device coupled in parallel to the series coupled pair of the first transistor and resistive device; and a second transistor coupled to the gate terminal of the power gate transistor and the ungated power supply node.
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公开(公告)号：US20170149427A1
公开(公告)日：2017-05-25
申请号：US14951343
申请日：2015-11-24
Applicant: Intel Corporation
Inventor： Yong Shim , Jaydeep P. Kulkarni , Pascal A. Meinerzhagen , Muhammad M. Khellah
IPC: H03K17/081 , H03K3/037 , H03K17/14
CPC classification number: H03K17/08104 , H03K3/0377 , H03K17/145 , H03K19/0016
Abstract: Described is an apparatus which comprises: a power gate transistor coupled to an ungated power supply node and a gated power supply node, the power gate transistor having a gate terminal; a resistive device; a first transistor coupled in series with the resistive device together forming a pair, the first transistor also coupled to the gate terminal of the power gate transistor; a capacitive device coupled in parallel to the series coupled pair of the first transistor and resistive device; and a second transistor coupled to the gate terminal of the power gate transistor and the ungated power supply node.
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