公开(公告)号：US20210048476A1

公开(公告)日：2021-02-18

申请号：US17085511

申请日：2020-10-30

Applicant: Intel IP Corporation

Inventor： Sankaran M. Menon ,  Bradley H. Smith ,  Jinshi Huang ,  Rolf H. Kuehnis

IPC: G01R31/3177 ,  H04W4/80 ,  G01R31/317

Abstract: Existing multi-wire debugging protocols, such as 4-wire JTAG, 2-wire cJTAG, or ARM SWD, are run through a serial wireless link by providing the debugger and the target device with hardware interfaces that include UARTs and conversion bridges. The debugger interface serializes outgoing control signals and de-serializes returning data. The target interface de-serializes incoming control signals and serializes outgoing data. The actions of the interfaces are transparent to the inner workings of the devices, allowing re-use of existing debugging software. Compression, signal combining, and other optional enhancements increase debugging speed and flexibility while wirelessly accessing target devices that may be too small, too difficult to reach, or too seal-dependent for a wired connection.

公开(公告)号：US20200348360A1

公开(公告)日：2020-11-05

申请号：US16947084

申请日：2020-07-17

Applicant: Intel IP Corporation

Inventor： Rolf H. Kuehnis ,  Sankaran M. Menon ,  Patrik Eder

IPC: G01R31/3177 ,  G01R31/317

Abstract: Techniques and mechanisms to exchange test, debug or trace (TDT) information via a general purpose input/output (I/O) interface. In an embodiment, an I/O interface of a device is coupled to an external TDT unit, wherein the I/O interface is compatible with an interconnect standard that supports communication of data other than any test information, debug information or trace information. One or more circuit components reside on the device or are otherwise coupled to the external TDT unit via the I/O interface. Information exchanged via the I/O interface is generated by, or results in, the performance of one or more TDT operations to evaluate the one or more circuit components. In another embodiment, the glue logic of the device interfaces the I/O interface with a test access point that is coupled between the one or more circuit components and the I/O interface.

公开(公告)号：US20180328987A1

公开(公告)日：2018-11-15

申请号：US15980409

申请日：2018-05-15

Applicant: Intel IP Corporation

Inventor： Sankaran M. Menon ,  Bradley H. Smith ,  Jinshi Huang ,  Rolf H. Kuehnis

IPC: G01R31/3177 ,  G01R31/317 ,  H04W4/80

CPC classification number: G01R31/3177 ,  G01R31/31703 ,  G01R31/31705 ,  G01R31/31722 ,  H04W4/80

Abstract: Existing multi-wire debugging protocols, such as 4-wire JTAG, 2-wire cJTAG, or ARM SWD, are run through a serial wireless link by providing the debugger and the target device with hardware interfaces that include UARTs and conversion bridges. The debugger interface serializes outgoing control signals and de-serializes returning data. The target interface de-serializes incoming control signals and serializes outgoing data. The actions of the interfaces are transparent to the inner workings of the devices, allowing re-use of existing debugging software. Compression, signal combining, and other optional enhancements increase debugging speed and flexibility while wirelessly accessing target devices that may be too small, too difficult to reach, or too seal-dependent for a wired connection.

公开(公告)号：US10054636B2

公开(公告)日：2018-08-21

申请号：US15085945

申请日：2016-03-30

Applicant: Intel IP Corporation

Inventor： Rolf H. Kuehnis ,  Sankaran M. Menon ,  Patrik Eder

IPC: G01R31/3177 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/31705 ,  G01R31/31715 ,  G01R31/31723

Abstract: Techniques and mechanisms to exchange test, debug or trace (TDT) information via a general purpose input/output (I/O) interface. In an embodiment, an I/O interface of a device is coupled to an external TDT unit, wherein the I/O interface is compatible with an interconnect standard that supports communication of data other than any test information, debug information or trace information. One or more circuit components reside on the device or are otherwise coupled to the external TDT unit via the I/O interface. Information exchanged via the I/O interface is generated by, or results in, the performance of one or more TDT operations to evaluate the one or more circuit components. In another embodiment, the glue logic of the device interfaces the I/O interface with a test access point that is coupled between the one or more circuit components and the I/O interface.

公开(公告)号：US10718812B2

公开(公告)日：2020-07-21

申请号：US16105748

申请日：2018-08-20

Applicant: Intel IP Corporation

Inventor： Rolf H. Kuehnis ,  Sankaran M. Menon ,  Patrik Eder

IPC: G01R31/3177 ,  G01R31/317

Abstract: Techniques and mechanisms to exchange test, debug or trace (TDT) information via a general purpose input/output (I/O) interface. In an embodiment, an I/O interface of a device is coupled to an external TDT unit, wherein the I/O interface is compatible with an interconnect standard that supports communication of data other than any test information, debug information or trace information. One or more circuit components reside on the device or are otherwise coupled to the external TDT unit via the I/O interface. Information exchanged via the I/O interface is generated by, or results in, the performance of one or more TDT operations to evaluate the one or more circuit components. In another embodiment, the glue logic of the device interfaces the I/O interface with a test access point that is coupled between the one or more circuit components and the I/O interface.

公开(公告)号：US09989592B2

公开(公告)日：2018-06-05

申请号：US14975685

申请日：2015-12-18

Applicant: Intel IP Corporation

Inventor： Sankaran M. Menon ,  Bradley H. Smith ,  Jinshi Huang ,  Rolf H. Kuehnis

IPC: G01R31/3177 ,  G01R31/317 ,  H04W4/00

CPC classification number: G01R31/3177 ,  G01R31/31703 ,  G01R31/31705 ,  G01R31/31722 ,  H04W4/80

Abstract: Existing multi-wire debugging protocols, such as 4-wire JTAG, 2-wire cJTAG, or ARM SWD, are run through a serial wireless link by providing the debugger and the target device with hardware interfaces that include UARTs and conversion bridges. The debugger interface serializes outgoing control signals and de-serializes returning data. The target interface de-serializes incoming control signals and serializes outgoing data. The actions of the interfaces are transparent to the inner workings of the devices, allowing re-use of existing debugging software. Compression, signal combining, and other optional enhancements increase debugging speed and flexibility while wirelessly accessing target devices that may be too small, too difficult to reach, or too seal-dependent for a wired connection.