公开(公告)号：US10831556B2

公开(公告)日：2020-11-10

申请号：US16064082

申请日：2015-12-23

Applicant: Intel IP Corporation

Inventor： Yuyang Du ,  Jian Sun ,  Yong Tong Chua ,  Mingqiu Sun ,  Sebastien Haezebrouck ,  Nicole Chalhoub ,  Premanand Sakarda ,  Richard Quinzio

IPC: G06F9/50 ,  G06F9/455

Abstract: Various systems and methods for virtual CPU consolidation to avoid physical CPU contention between virtual machines are described herein. A processor system that includes multiple physical processors (PCPUs) includes a first virtual machine (VM) that includes multiple first virtual processors (VCPUs); a second VM that includes multiple second VCPUs; and a virtual machine monitor (VMM) to map individual ones of the first VCPUs to run on at least one of, individual PCPUs of a first subset of the PCPUs and individual PCPUs of a set of PCPUs that includes the first subset of the PCPUs and a second subset of the PCPUs, based at least in part upon compute capacity of the first subset of the PCPUs to run the first VCPUs, and to map individual ones of the second VCPUs to run on individual ones of the second subset of the PCPUs.

公开(公告)号：US20190004866A1

公开(公告)日：2019-01-03

申请号：US16064082

申请日：2015-12-23

Applicant: Intel IP Corporation

Inventor： Yuyang Du ,  Jian Sun ,  Yong Tong Chua ,  Mingqui Sun ,  Sebastien Haezebrouck ,  Nicole Chalhoub ,  Premanand Sakarda ,  Richard Quinzio

IPC: G06F9/50 ,  G06F9/455

CPC classification number: G06F9/5077 ,  G06F9/45558 ,  G06F9/505 ,  G06F9/5066 ,  G06F2009/4557 ,  G06F2009/45579

Abstract: Various systems and methods for virtual CPU consolidation to avoid physical CPU contention between virtual machines are described herein. A processor system that includes multiple physical processors (PCPUs) includes a first virtual machine (VM) that includes multiple first virtual processors (VCPUs); a second VM that includes multiple second VCPUs; and a virtual machine monitor (VMM) to map individual ones of the first VCPUs to run on at least one of, individual PCPUs of a first subset of the PCPUs and individual PCPUs of a set of PCPUs that includes the first subset of the PCPUs and a second subset of the PCPUs, based at least in part upon compute capacity of the first subset of the PCPUs to run the first VCPUs, and to map individual ones of the second VCPUs to run on individual ones of the second subset of the PCPUs.