公开(公告)号：US20200021274A1

公开(公告)日：2020-01-16

申请号：US16474563

申请日：2017-03-31

Applicant: Intel IP Corporation

Inventor： Michael Wagner ,  Stephan Leuschner

IPC: H03H9/60 ,  H03H7/01 ,  H03H9/54 ,  H03H9/02

Abstract: Examples provide a wideband filter structure and apparatus, a radio transceiver, a mobile terminal, and a method for filtering a radio signal. The wideband filter structure (10) for a radio signal comprises a combination of at least one acoustic resonator (12) and at least one analog resonator (14). The acoustic resonator (12) is coupled to the analog resonator (14). The wideband filter structure (10) comprises a further component (16), which is coupled to the combination of the acoustic resonator (12) and the analog resonator (14).

公开(公告)号：US20170179917A1

公开(公告)日：2017-06-22

申请号：US14978231

申请日：2015-12-22

Applicant: Intel IP Corporation

Inventor： Stephan Leuschner ,  Jose Pedro Diogo Faisca Moreira

IPC: H03H7/38 ,  H03H7/01

CPC classification number: H03H7/38 ,  H01F27/2804 ,  H01L23/645 ,  H04B1/0458

Abstract: A communication matching network for multi-harmonic suppression includes a communication circuit configured to provide a signal. The communication matching network further includes a matching circuit configured to receive the signal from the communication circuit and suppress one or more harmonics of the received signal to generate a filtered signal, wherein the matching circuit includes a transformer comprising a first winding and a second winding, wherein the first winding includes a first inductance and the second winding includes a second inductance and wherein the matching network includes a harmonic trap including a third inductance such that the third inductance is located inside or within a physical layout of the first winding and/or the second winding. The communication matching network further includes a receiver circuit configured to receive the filtered signal from the matching circuit for further processing.

公开(公告)号：US20180331769A1

公开(公告)日：2018-11-15

申请号：US15776083

申请日：2016-10-21

Applicant: Intel IP Corporation

Inventor： Stephan Leuschner ,  Peter Pfann

IPC: H04B15/00 ,  H04B1/525 ,  H04B15/04 ,  H01F27/28 ,  H01F27/38

CPC classification number: H04B15/005 ,  H01F27/28 ,  H01F27/385 ,  H04B1/525 ,  H04B15/04

Abstract: An apparatus for reducing a magnetic coupling between a first electronic circuit and a second electronic circuit is provided. The apparatus includes a conductor loop enclosing the first electronic circuit or the second electronic circuit, and a tuning element coupled to the conductor loop. The conductor loop and the tuning element form a resonant circuit, wherein the tuning element is configured to adjust a resonance frequency of the resonant circuit to a frequency related to a frequency of a signal processed by the second electronic circuit.

公开(公告)号：US09979375B2

公开(公告)日：2018-05-22

申请号：US14978231

申请日：2015-12-22

Applicant: Intel IP Corporation

Inventor： Stephan Leuschner ,  Jose Pedro Diogo Faisca Moreira

IPC: H03H7/38 ,  H03H7/01 ,  H01F27/28 ,  H01L23/64 ,  H04B1/04

CPC classification number: H03H7/38 ,  H01F27/2804 ,  H01L23/645 ,  H04B1/0458

Abstract: A communication matching network for multi-harmonic suppression includes a communication circuit configured to provide a signal. The communication matching network further includes a matching circuit configured to receive the signal from the communication circuit and suppress one or more harmonics of the received signal to generate a filtered signal, wherein the matching circuit includes a transformer comprising a first winding and a second winding, wherein the first winding includes a first inductance and the second winding includes a second inductance and wherein the matching network includes a harmonic trap including a third inductance such that the third inductance is located inside or within a physical layout of the first winding and/or the second winding. The communication matching network further includes a receiver circuit configured to receive the filtered signal from the matching circuit for further processing.

公开(公告)号：US09490834B2

公开(公告)日：2016-11-08

申请号：US15048143

申请日：2016-02-19

Applicant: Intel IP Corporation

Inventor： Stephan Leuschner ,  Michael Fulde ,  Daniel Sira ,  Gerhard Knoblinger

IPC: H03M1/66

CPC classification number: H03M1/66 ,  H03M1/662

Abstract: A digital-to-analog converter circuit including a plurality of digital-to-analog converter cells is provided. A first digital-to-analog converter cell of the plurality of digital-to-analog converter cells includes a cell control module configured to provide alternatingly a first voltage and a second voltage to a first electrode of a capacitive element of the first digital-to-analog converter cell based on a digital input signal during a predefined time interval. A second digital-to-analog converter cell of the plurality of digital-to-analog converter cells includes a cell control module configured to provide a third voltage to a first electrode of a capacitive element of the second digital-to-analog converter cell during the predefined time interval. The first voltage is higher than an upper threshold voltage corresponding to a first digital threshold level of the digital input signal and the second voltage is lower than a lower threshold voltage corresponding to a second digital threshold level of the digital input signal. The third voltage is constantly between the upper threshold voltage and the lower threshold voltage.

Abstract translation: 提供了包括多个数模转换器单元的数模转换器电路。 多个数模转换器单元中的第一数模转换器单元包括单元控制模块，其被配置为交替地向第一数字到第一数模转换单元的电容元件的第一电极提供第一电压和第二电压， 基于数字输入信号在预定义的时间间隔内。 多个数模转换器单元的第二数模转换器单元包括单元控制模块，其被配置为在第二数模转换器单元的电容元件的第一电极处提供第三电压 预定义的时间间隔。 第一电压高于对应于数字输入信号的第一数字阈值电平的上阈值电压，而第二电压低于对应于数字输入信号的第二数字阈值电平的下阈值电压。 第三电压恒定在上阈值电压和较低阈值电压之间。

公开(公告)号：US11050411B2

公开(公告)日：2021-06-29

申请号：US16474563

申请日：2017-03-31

Applicant: Intel IP Corporation

Inventor： Michael Wagner ,  Stephan Leuschner

IPC: H03H9/54 ,  H03H7/01 ,  H03H9/02 ,  H03H9/60

Abstract: Examples provide a wideband filter structure and apparatus, a radio transceiver, a mobile terminal, and a method for filtering a radio signal. The wideband filter structure (10) for a radio signal comprises a combination of at least one acoustic resonator (12) and at least one analog resonator (14). The acoustic resonator (12) is coupled to the analog resonator (14). The wideband filter structure (10) comprises a further component (16), which is coupled to the combination of the acoustic resonator (12) and the analog resonator (14).

公开(公告)号：US10333630B2

公开(公告)日：2019-06-25

申请号：US15776083

申请日：2016-10-21

Applicant: Intel IP Corporation

Inventor： Stephan Leuschner ,  Peter Pfann

IPC: H04B15/00 ,  H04B1/525 ,  H04B15/04 ,  H01F27/28 ,  H01F27/38

Abstract: An apparatus for reducing a magnetic coupling between a first electronic circuit and a second electronic circuit is provided. The apparatus includes a conductor loop enclosing the first electronic circuit or the second electronic circuit, and a tuning element coupled to the conductor loop. The conductor loop and the tuning element form a resonant circuit, wherein the tuning element is configured to adjust a resonance frequency of the resonant circuit to a frequency related to a frequency of a signal processed by the second electronic circuit.

公开(公告)号：US20180241368A1

公开(公告)日：2018-08-23

申请号：US15926360

申请日：2018-03-20

Applicant: Intel IP Corporation

Inventor： Stephan Leuschner ,  Jose Pedro Diogo Faisca Moreira

IPC: H03H7/38 ,  H01L23/64

CPC classification number: H03H7/38 ,  H01F27/2804 ,  H01L23/645 ,  H04B1/0458

Abstract: A communication matching network for multi-harmonic suppression includes a communication circuit configured to provide a signal. The communication matching network further includes a matching circuit configured to receive the signal from the communication circuit and suppress one or more harmonics of the received signal to generate a filtered signal, wherein the matching circuit includes a transformer comprising a first winding and a second winding, wherein the first winding includes a first inductance and the second winding includes a second inductance and wherein the matching network includes a harmonic trap including a third inductance such that the third inductance is located inside or within a physical layout of the first winding and/or the second winding. The communication matching network further includes a receiver circuit configured to receive the filtered signal from the matching circuit for further processing.

公开(公告)号：US20160285470A1

公开(公告)日：2016-09-29

申请号：US15048143

申请日：2016-02-19

Applicant: Intel IP Corporation

Inventor： Stephan Leuschner ,  Michael Fulde ,  Daniel Sira ,  Gerhard Knoblinger

IPC: H03M1/66

CPC classification number: H03M1/66 ,  H03M1/662

Abstract: A digital-to-analog converter circuit including a plurality of digital-to-analog converter cells is provided. A first digital-to-analog converter cell of the plurality of digital-to-analog converter cells includes a cell control module configured to provide alternatingly a first voltage and a second voltage to a first electrode of a capacitive element of the first digital-to-analog converter cell based on a digital input signal during a predefined time interval. A second digital-to-analog converter cell of the plurality of digital-to-analog converter cells includes a cell control module configured to provide a third voltage to a first electrode of a capacitive element of the second digital-to-analog converter cell during the predefined time interval. The first voltage is higher than an upper threshold voltage corresponding to a first digital threshold level of the digital input signal and the second voltage is lower than a lower threshold voltage corresponding to a second digital threshold level of the digital input signal. The third voltage is constantly between the upper threshold voltage and the lower threshold voltage.

Abstract translation: 提供了包括多个数模转换器单元的数模转换器电路。 多个数模转换器单元中的第一数模转换器单元包括单元控制模块，其被配置为交替地向第一数字到第一数模转换单元的电容元件的第一电极提供第一电压和第二电压， 基于数字输入信号在预定义的时间间隔内。 多个数模转换器单元的第二数模转换器单元包括单元控制模块，其被配置为在第二数模转换器单元的电容元件的第一电极处提供第三电压 预定义的时间间隔。 第一电压高于对应于数字输入信号的第一数字阈值电平的上阈值电压，而第二电压低于对应于数字输入信号的第二数字阈值电平的下阈值电压。 第三电压恒定在上阈值电压和较低阈值电压之间。