公开(公告)号：US20170207157A1

公开(公告)日：2017-07-20

申请号：US15375241

申请日：2016-12-12

Applicant: J-DEVICES CORPORATION

Inventor： Kiyoaki HASHIMOTO ,  Yuko YAMAMOTO

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/30 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24195 ,  H01L2224/29195 ,  H01L2224/32225 ,  H01L2224/83005 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2224/96 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3511

Abstract: A method for manufacturing a semiconductor package includes: forming an insulating layer on a support plate; forming a via in the insulating layer; locating a semiconductor device on the insulating layer such that an electrode of the semiconductor device is on the via; removing the support plate; forming a seed layer on a surface of the insulating layer opposite to the semiconductor device, in the via, and on a surface of the electrode of the semiconductor device; and forming a metal layer in the via.