公开(公告)号：US09899993B2

公开(公告)日：2018-02-20

申请号：US14913309

申请日：2014-07-29

Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY

Inventor： Hidetoshi Onodera ,  Islam A. K. M Mahfuzul

IPC: H03K5/134 ,  G01R31/28 ,  H03K5/00

CPC classification number: H03K5/134 ,  G01R31/2882 ,  H03K2005/00019

Abstract: A delay circuit contains a first inversion circuit including a pull-up circuit and a pull-down circuit, and a second inversion circuit including a pull-up circuit and a pull-down circuit. The delay circuit further contains a first pass transistor connected in series to the pull-up circuit in the first inversion circuit between a power supply potential and an output node, a second pass transistor connected in series to the pull-down circuit in the first inversion circuit between a ground potential and the output node, a third pass transistor connected in series between the input node and the pull-up circuit in the second inversion circuit, and a fourth pass transistor connected in series between the input node and the pull-down circuit in the second inversion circuit. A delay characteristic of the delay circuit is changed by a combination of control signals applied to gates of the pass transistors.