公开(公告)号：US07551323B2

公开(公告)日：2009-06-23

申请号：US10414854

申请日：2003-04-16

Applicant: James Ray Bailey ,  Curt Paul Breswick ,  David Allen Crutchfield ,  Ronald Edward Garnett ,  Bob Thai Pham ,  James Alan Ward

Inventor： James Ray Bailey ,  Curt Paul Breswick ,  David Allen Crutchfield ,  Ronald Edward Garnett ,  Bob Thai Pham ,  James Alan Ward

IPC: H04N1/56 ,  H04N1/60

CPC classification number: H04N1/52 ,  H04N1/4052

Abstract: Error diffusion is performed upon input image data. In one aspect, multiple error diffusion processing elements perform error diffusion on a selected pixel in parallel. In another aspect, the error diffusion logic is integrally formed with a fast local memory in the same electronic device, such as an ASIC. The error data produced by the error diffusion logic for a pixel is buffered in the fast local memory until it is to be used by the error diffusion logic on other pixels. In still another aspect, a first-in-first-out (FIFO) buffer regulates or buffers the color image data between the output of a color conversion system, such as a colorant lookup table, and the input an error diffusion processing element. In yet another aspect, the error diffusion logic has tagging logic that produces and stores an indicator, either in the output data stream itself or in a separate area, to indicate whether a raster contains printable data.

Abstract translation: 对输入图像数据执行误差扩散。 在一个方面，多个误差扩散处理元件并行地对所选择的像素执行误差扩散。 在另一方面，误差扩散逻辑与同一电子设备（例如ASIC）中的快速本地存储器整体形成。 由像素的误差扩散逻辑产生的误差数据被缓冲在快速本地存储器中，直到其被其它像素上的误差扩散逻辑使用。 在另一方面，先入先出（FIFO）缓冲器在诸如着色查找表的颜色转换系统的输出和输入误差扩散处理元件之间调节或缓冲彩色图像数据。 在另一方面，误差扩散逻辑具有标记逻辑，该标签逻辑在输出数据流本身中或在单独的区域中产生和存储指示符，以指示光栅是否包含可打印数据。

公开(公告)号：US20120144256A1

公开(公告)日：2012-06-07

申请号：US13308286

申请日：2011-11-30

Applicant: James Ray Bailey ,  Christopher W. Case ,  James Patrick Sharpe ,  James Alan Ward ,  Michael Anthony Marra, III

Inventor： James Ray Bailey ,  Christopher W. Case ,  James Patrick Sharpe ,  James Alan Ward ,  Michael Anthony Marra, III

IPC: G01R31/3177 ,  G06F11/25

CPC classification number: G06F11/25 ,  G01R31/3177 ,  G06F11/2294 ,  G06F11/26 ,  G06F11/273

Abstract: A system for testing or debugging a device under test having an embedded logic analyzer. In one embodiment, the system includes software stored in non-transitory memory for testing a device under test having an embedded logic analyzer, the software program product having instructions which, when executed by a computing device associated with the device under test cause the computing device to reconstruct signals of interest in the device under test based at least in part upon signals captured by the embedded logic analyzer during the test or debug session, and cause the computing device to display the reconstructed signals of interest to a user of the computing device.

Abstract translation: 用于测试或调试具有嵌入式逻辑分析仪的被测器件的系统。 在一个实施例中，系统包括存储在非瞬时存储器中的软件，用于测试具有嵌入式逻辑分析器的被测器件，该软件程序产品具有指令，当与被测器件相关联的计算设备执行时，该指令导致计算设备 至少部分地基于在测试或调试会话期间由嵌入式逻辑分析器捕获的信号来重建被测器件中感兴趣的信号，并使计算设备向计算设备的用户显示感兴趣的重构信号。

公开(公告)号：US09170901B2

公开(公告)日：2015-10-27

申请号：US13308286

申请日：2011-11-30

Applicant: James Ray Bailey ,  Christopher W Case ,  James Patrick Sharpe ,  James Alan Ward ,  Michael Anthony Marra, III

Inventor： James Ray Bailey ,  Christopher W Case ,  James Patrick Sharpe ,  James Alan Ward ,  Michael Anthony Marra, III

IPC: G06F11/00 ,  G06F11/25 ,  G06F11/26 ,  G06F11/273 ,  G01R31/3177 ,  G06F11/22

CPC classification number: G06F11/25 ,  G01R31/3177 ,  G06F11/2294 ,  G06F11/26 ,  G06F11/273

Abstract: A system for testing or debugging a device under test having an embedded logic analyzer. In one embodiment, the system includes software stored in non-transitory memory for testing a device under test having an embedded logic analyzer, the software program product having instructions which, when executed by a computing device associated with the device under test cause the computing device to reconstruct signals of interest in the device under test based at least in part upon signals captured by the embedded logic analyzer during the test or debug session, and cause the computing device to display the reconstructed signals of interest to a user of the computing device.

Abstract translation: 用于测试或调试具有嵌入式逻辑分析仪的被测器件的系统。 在一个实施例中，系统包括存储在非瞬时存储器中的软件，用于测试具有嵌入式逻辑分析器的被测器件，该软件程序产品具有指令，当与被测器件相关联的计算设备执行时，该指令导致计算设备 至少部分地基于在测试或调试会话期间由嵌入式逻辑分析器捕获的信号来重建被测器件中感兴趣的信号，并使计算设备向计算设备的用户显示感兴趣的重构信号。

公开(公告)号：US20110047424A1

公开(公告)日：2011-02-24

申请号：US12542976

申请日：2009-08-18

Applicant: James Ray Bailey ,  James Alan Ward

Inventor： James Ray Bailey ,  James Alan Ward

IPC: G01R31/3177 ,  G06F11/00

CPC classification number: G06F11/2294

Abstract: An integrated circuit including a logic analyzer with enhanced analyzing and debugging capabilities and a method therefor. In one embodiment of the present invention, an embedded logic analyzer (ELA) receives a plurality of signals from a plurality of buses within an integrated circuit (IC). The ELA includes an interconnect module to select a trigger signal and/or a sampled signal from the plurality of received signals. A trigger module sets at least one trigger condition and detects if the trigger signal satisfies the at least one trigger condition. When the trigger condition is satisfied, an output module performs at least one task based upon the satisfied at least one trigger condition. If a sampling process is initiated by the output module, the plurality of sampled signals is sampled and may be stored in a memory. The capability of the output module to perform multiple user-defined tasks enhances the debugging capability of the ELA and makes it more versatile.

Abstract translation: 一种集成电路，包括具有增强的分析和调试能力的逻辑分析仪及其方法。 在本发明的一个实施例中，嵌入式逻辑分析器（ELA）从集成电路（IC）内的多个总线接收多个信号。 ELA包括互连模块，用于从多个接收信号中选择触发信号和/或采样信号。 触发模块设置至少一个触发条件，并检测触发信号是否满足至少一个触发条件。 当满足触发条件时，输出模块基于满足的至少一个触发条件来执行至少一个任务。 如果由输出模块启动采样处理，则对采样的多个信号进行采样并将其存储在存储器中。 输出模块执行多个用户定义任务的能力增强了ELA的调试能力，使其更加通用。

公开(公告)号：US20160011953A1

公开(公告)日：2016-01-14

申请号：US14547745

申请日：2014-11-19

Applicant: James Ray Bailey

Inventor： James Ray Bailey

IPC: G06F11/263 ,  G01R31/3177

CPC classification number: G06F11/263 ,  G01R31/31705 ,  G01R31/3177 ,  G06F11/2294

Abstract: An integrated circuit including a logic analyzer with enhanced analyzing and debugging capabilities and a method therefor. In one embodiment of the present invention, an embedded logic analyzer (ELA) receives a plurality of signals from a plurality of buses within an integrated circuit (IC). The ELA includes an interconnect module to select a trigger signal and/or a sampled signal from the plurality of received signals. A trigger module sets at least one trigger condition and detects if the trigger signal satisfies the at least one trigger condition. When the trigger condition is satisfied, an output module performs at least one task based upon the satisfied at least one trigger condition. If a sampling process is initiated by the output module, the plurality of sampled signals is sampled and may be stored in a memory. The capability of the output module to perform multiple user-defined tasks enhances the debugging capability of the ELA and makes it more versatile.

Abstract translation: 一种集成电路，包括具有增强的分析和调试能力的逻辑分析仪及其方法。 在本发明的一个实施例中，嵌入式逻辑分析器（ELA）从集成电路（IC）内的多个总线接收多个信号。 ELA包括互连模块，用于从多个接收信号中选择触发信号和/或采样信号。 触发模块设置至少一个触发条件，并检测触发信号是否满足至少一个触发条件。 当满足触发条件时，输出模块基于满足的至少一个触发条件来执行至少一个任务。 如果由输出模块启动采样处理，则对采样的多个信号进行采样并将其存储在存储器中。 输出模块执行多个用户定义任务的能力增强了ELA的调试能力，使其更加通用。

公开(公告)号：US08516304B2

公开(公告)日：2013-08-20

申请号：US12877846

申请日：2010-09-08

Applicant: James Ray Bailey ,  Christopher Wilson Case ,  James Patrick Sharpe

Inventor： James Ray Bailey ,  Christopher Wilson Case ,  James Patrick Sharpe

IPC: G06F11/00

CPC classification number: G01R31/3177 ,  G06F11/2294

Abstract: An integrated circuit including a logic analyzer with enhanced analyzing and debugging capabilities and a method therefore. In one embodiment, an integrated circuit includes a logic analyzer having a first input receiving a plurality of signals and an output for providing an indication of a detection, by the logic analyzer, of at least one trigger event; and a built in self test block having a first input for receiving one or more of the signals appearing at the first input of the logic analyzer, a second input coupled to the output of the logic analyzer for selectively enabling the BIST block, the BIST block generating and maintaining a signature based upon the first and second inputs thereof.

Abstract translation: 包括具有增强的分析和调试功能的逻辑分析仪的集成电路及其方法。 在一个实施例中，集成电路包括具有接收多个信号的第一输入的逻辑分析器和用于通过逻辑分析仪提供对至少一个触发事件的检测指示的输出; 以及内置自测试块，其具有用于接收出现在所述逻辑分析仪的第一输入端的一个或多个信号的第一输入;耦合到所述逻辑分析器的输出的第二输入，用于选择性地启用所述BIST块，所述BIST块 基于其第一和第二输入产生和维护签名。

公开(公告)号：US20110047423A1

公开(公告)日：2011-02-24

申请号：US12877819

申请日：2010-09-08

Applicant: James Ray Bailey

Inventor： James Ray Bailey

IPC: G01R31/3177 ,  G06F11/25

CPC classification number: G06F11/263 ,  G01R31/31705 ,  G01R31/3177 ,  G06F11/2294

Abstract: An integrated circuit including a logic analyzer with enhanced analyzing and debugging capabilities and a method therefor. In one embodiment of the present invention, an embedded logic analyzer (ELA) receives a plurality of signals from a plurality of buses within an integrated circuit (IC). The ELA includes an interconnect module to select a trigger signal and/or a sampled signal from the plurality of received signals. A trigger module sets at least one trigger condition and detects if the trigger signal satisfies the at least one trigger condition. When the trigger condition is satisfied, an output module performs at least one task based upon the satisfied at least one trigger condition. If a sampling process is initiated by the output module, the plurality of sampled signals is sampled and may be stored in a memory. The capability of the output module to perform multiple user-defined tasks enhances the debugging capability of the ELA and makes it more versatile.

Abstract translation: 一种集成电路，包括具有增强的分析和调试能力的逻辑分析仪及其方法。 在本发明的一个实施例中，嵌入式逻辑分析器（ELA）从集成电路（IC）内的多个总线接收多个信号。 ELA包括互连模块，用于从多个接收信号中选择触发信号和/或采样信号。 触发模块设置至少一个触发条件，并检测触发信号是否满足至少一个触发条件。 当满足触发条件时，输出模块基于满足的至少一个触发条件来执行至少一个任务。 如果由输出模块启动采样处理，则对采样的多个信号进行采样并将其存储在存储器中。 输出模块执行多个用户定义任务的能力增强了ELA的调试能力，使其更加通用。

公开(公告)号：US07480071B2

公开(公告)日：2009-01-20

申请号：US10413201

申请日：2003-04-14

Applicant: James Ray Bailey ,  Joseph Yackzan

Inventor： James Ray Bailey ,  Joseph Yackzan

IPC: G06F15/00 ,  G06K1/00 ,  G03F3/08 ,  H04N1/409

CPC classification number: G06T3/4007

Abstract: Lines of input image data are scaled in a first dimension, the one-dimensionally scaled lines are stored in a buffer memory until a sufficient number of lines have been stored to perform scaling equally in two dimensions, and the stored lines are then scaled in a second dimension to produce image data scaled two-dimensionally by a user-selected scaling percentage. A first image scaling method is used to scale the input image data if the user-selected scaling percentage exceeds a predetermined threshold value, such as 50 percent, and a second scaling method is used if the scaling percentage does not exceed the threshold value. The first method can be, for example, linear interpolation, and the second method can be, for example, averaging.

Abstract translation: 输入图像数据的行在第一维度上缩放，一维缩放的行被存储在缓冲存储器中，直到已经存储了足够数量的行以在两维中同等地执行缩放，然后将存储的行在 第二维以产生通过用户选择的缩放百分比二维缩放的图像数据。 如果用户选择的缩放百分比超过预定阈值（例如50％），则第一图像缩放方法用于缩放输入图像数据，并且如果缩放百分比不超过阈值，则使用第二缩放方法。 第一种方法可以是例如线性插值，第二种方法可以是例如平均化。

公开(公告)号：US20080235501A1

公开(公告)日：2008-09-25

申请号：US11687911

申请日：2007-03-19

Applicant: James Ray Bailey ,  Christopher Wilson Case ,  Vladimir Vinogradov

Inventor： James Ray Bailey ,  Christopher Wilson Case ,  Vladimir Vinogradov

IPC: G06F9/24

CPC classification number: G06F11/1417 ,  G06F11/1004

Abstract: A method for detecting and correcting firmware corruption in a system having a host communicatively coupled to an electronic apparatus, the electronic apparatus having a hardware unit communicatively coupled to a non-volatile memory, includes determining via the hardware unit whether firmware on the non-volatile memory is corrupted; if the firmware is determined to be corrupted, then: invoking a communication driver resident in the hardware unit to establish bi-directional communications between the host and the electronic apparatus; and initiating a firmware download from the host to update the firmware on the non-volatile memory to an uncorrupted state.

Abstract translation: 一种用于在具有通信地耦合到电子设备的主机的系统中检测和校正固件损坏的方法，所述电子设备具有通信地耦合到非易失性存储器的硬件​​单元，包括经由所述硬件单元确定所述非易失性存储器上的固件 记忆被破坏了 如果确定固件被破坏，则：调用驻留在硬件单元中的通信驱动程序，以建立主机与电子设备之间的双向通信; 并且从主机发起固件下载以将非易失性存储器上的固件更新为未被破坏的状态。

公开(公告)号：US08103712B2

公开(公告)日：2012-01-24

申请号：US11863711

申请日：2007-09-28

Applicant: James Ray Bailey ,  Zachary Nathan Fister ,  Jimmy Daniel Moore, Jr.

Inventor： James Ray Bailey ,  Zachary Nathan Fister ,  Jimmy Daniel Moore, Jr.

IPC: G06F7/535

CPC classification number: G06F7/535 ,  G06F2207/5355

Abstract: A method for performing a division operation in a system includes a) determining an approximate quotient of a numerator value and a denominator value; b) determining an initial error of the approximate quotient; c) determining a quotient adjustment value based on the initial error; d) determining whether to apply the quotient adjustment value to the approximate quotient; e) if the determination at d) is YES, then applying the quotient adjustment value to the approximate quotient; f) determining an iterative error of the approximate quotient; g) updating the quotient adjustment value based on the iterative error; h) repeating acts d) through g) until the determination at d) is NO, thereby determining a final value for the approximate quotient; i) generating an integer quotient based on the final value of the approximate quotient; and j) using the integer quotient with regard to at least one aspect of the system.

Abstract translation: 一种用于在系统中执行除法运算的方法包括：a）确定分子值和分母值的近似商; b）确定近似商的初始误差; c）基于初始误差确定商调整值; d）确定是否将商调整值应用于近似商; e）如果d）的确定为YES，则将商调整值应用于近似商; f）确定近似商的迭代误差; g）基于迭代误差来更新商调整值; h）重复d）到g）直到d）的确定为否，从而确定近似商的最终值; i）基于近似商的最终值生成整数商; 和j）使用关于系统的至少一个方面的整数商。