公开(公告)号：US20250157890A1

公开(公告)日：2025-05-15

申请号：US18945958

申请日：2024-11-13

Applicant: Japan Display Inc.

Inventor： Takamitsu FUJIMOTO ,  Kenji HARADA ,  Takayuki SUZUKI

IPC: H01L23/48 ,  H01L27/092 ,  H01L29/423

Abstract: A semiconductor device according to an embodiment of the present invention includes: a first semiconductor layer; a first gate electrode facing the first semiconductor layer; a second gate electrode facing the first semiconductor layer and supplied with the same voltage as the first gate electrode; a first gate insulating layer between the first semiconductor layer and the first gate electrode, and between the first semiconductor layer and the second gate electrode; a second semiconductor layer sandwiching the first gate electrode with the first semiconductor layer; a third gate electrode facing the second semiconductor layer on an opposite side to the first gate electrode with respect to the second semiconductor layer, and overlapping the first gate electrode in a plan view; and a second gate insulating layer between the second semiconductor layer and the third gate electrode.

公开(公告)号：US20250081750A1

公开(公告)日：2025-03-06

申请号：US18796306

申请日：2024-08-07

Applicant: Japan Display Inc.

Inventor： Kazuyuki HARADA ,  Hiroshi TABATAKE ,  Hideyuki TAKAHASHI ,  Takamitsu FUJIMOTO

IPC: H10K59/122 ,  H10K59/88

Abstract: According to one embodiment, a display device includes a partition which is provided between each adjacent pair of display elements in a display area, an electrode layer provided in a surrounding area, a conductive layer provided above the electrode layer, and an inorganic insulating layer provided between the electrode layer and the conductive layer. The partition and the conductive layer include a conductive lower portion and an upper portion which protrudes from side surfaces of the lower portion. The electrode layer includes an electrode aperture penetrating in a stacking direction. The conductive layer overlaps with the electrode aperture.

公开(公告)号：US20160124257A1

公开(公告)日：2016-05-05

申请号：US14993235

申请日：2016-01-12

Applicant: JAPAN DISPLAY INC.

Inventor： Takamitsu FUJIMOTO

IPC: G02F1/1345 ,  G02F1/1362 ,  G02F1/1333

CPC classification number: G02F1/1345 ,  G02F1/133345 ,  G02F1/136204 ,  G02F1/136286

Abstract: In one embodiment, an array substrate includes an active area in the shape of a rectangle, and first, second third and fourth end portions, surrounding the active area. A source control circuit is electrically connected with one end of the source lines drawn to the third end portion from the active area. First and second common terminals of a common potential are formed in the first end portion. A power supply line is electrically connected with the first common terminal and extends along the second, third and fourth end portions in this order, and connected with the second common terminal. A branch wiring is electrically connected with an intermediate portion of the electric power supply line and the source control circuit, and extending in the first direction.