公开(公告)号：US10950192B2

公开(公告)日：2021-03-16

申请号：US16298581

申请日：2019-03-11

Applicant: Japan Display Inc.

Inventor： Yutaka Mitsuzawa

IPC: G09G3/36

Abstract: According to an aspect, a display device includes: a plurality of sub-pixels, each sub-pixel including at least one memory; a setting circuit configured to select either a first mode in which a still image is displayed or a second mode in which a moving image is displayed; and a switching circuit configured to switch coupling between the sub-pixels and the memories according to the selection made by the setting circuit. The first mode is a mode in which each of the sub-pixels is coupled to one of the at least one memory included in the sub-pixel, and the second mode is a mode including a time period in which at least one of the sub-pixels is coupled to the at least one memory included in another of the sub-pixels.

公开(公告)号：US10885859B2

公开(公告)日：2021-01-05

申请号：US16393533

申请日：2019-04-24

Applicant: Japan Display Inc.

Inventor： Yutaka Mitsuzawa

IPC: G09G3/20 ,  G09G3/36

Abstract: A display device includes: a display unit including pixels each including a holding circuit that holds a pixel signal; a driver that drives the pixels based on image signals and supply the pixel signal to the holding circuit of each pixel; an encoding circuit that encodes the image signals on a frame basis; storage that stores data resulting from encoding; a determination circuit that determines whether the image signals for consecutive frames are moving image signals or still image signals; and a controller that controls the driver based on the image signals and the result of the determination circuit. The controller brings the driver into a first state for driving the pixels based on the image signals when the result indicates the moving image signals, and into a second state for causing at least part of the driver to stop operating when the result indicates the still image signals.

公开(公告)号：US11195488B2

公开(公告)日：2021-12-07

申请号：US16932306

申请日：2020-07-17

Applicant: Japan Display Inc.

Inventor： Masashi Mitsui ,  Susumu Kimura ,  Yutaka Mitsuzawa

IPC: G09G3/36

Abstract: According to an aspect, a display device includes: sub-pixels arranged in row and column directions and each including a memory block including memories to store therein sub-pixel data; memory selection line groups corresponding to rows and each including memory selection lines electrically coupled to the memory blocks in the respective sub-pixels that belong to the corresponding row; and a memory selection circuit configured to concurrently output a memory selection signal to the memory selection line groups. Each sub-pixel displays an image based on the sub-pixel data stored in one of the memories in accordance with the memory selection line supplied with the memory selection signal. The number of times that the set value is changed is less than the number of times that images are switched from one to another based on the memory selection signal output from the memory selection circuit.

公开(公告)号：US20200273420A1

公开(公告)日：2020-08-27

申请号：US16872771

申请日：2020-05-12

Applicant: Japan Display Inc.

Inventor： Yutaka Mitsuzawa ,  Takayuki Nakao ,  Masaya Tamaki ,  Yutaka Ozawa

IPC: G09G3/36

Abstract: A display device includes: a plurality of sub-pixels each including a memory block that includes a plurality of memories each of which is configured to store sub-pixel data; a plurality of memory selection line groups provided to respective rows and each including a plurality of memory selection lines electrically coupled to the corresponding memory blocks in the sub-pixels that belong to a corresponding row; a memory selection circuit configured to simultaneously output a memory selection signal to the memory selection line groups, the memory selection signal being a signal for selecting one from the plurality of memories in each of the memory blocks. In accordance with the memory selection lines supplied with the memory selection signal, the sub-pixels display an image based on the sub-pixel data stored in memories in the respective sub-pixels, the memories each being one of the plurality of memories in the corresponding sub-pixel.

公开(公告)号：US20190114983A1

公开(公告)日：2019-04-18

申请号：US16157291

申请日：2018-10-11

Applicant: Japan Display Inc.

Inventor： Masashi Mitsui ,  Susumu Kimura ,  Yutaka Mitsuzawa

IPC: G09G3/36

Abstract: According to an aspect, a display device includes: sub-pixels arranged in row and column directions and each including a memory block including memories to store therein sub-pixel data; memory selection line groups corresponding to rows and each including memory selection lines electrically coupled to the memory blocks in the respective sub-pixels that belong to the corresponding row; and a memory selection circuit configured to concurrently output a memory selection signal to the memory selection line groups. Each sub-pixel displays an image based on the sub-pixel data stored in one of the memories in accordance with the memory selection line supplied with the memory selection signal. The number of times that the set value is changed is less than the number of times that images are switched from one to another based on the memory selection signal output from the memory selection circuit.

公开(公告)号：US11217191B2

公开(公告)日：2022-01-04

申请号：US17175053

申请日：2021-02-12

Applicant: Japan Display Inc.

Inventor： Yutaka Mitsuzawa

IPC: G09G3/36

Abstract: According to an aspect, a display device includes: a plurality of sub-pixels, each sub-pixel including at least one memory; a setting circuit configured to select either a first mode in which a still image is displayed or a second mode in which a moving image is displayed; and a switching circuit configured to switch coupling between the sub-pixels and the memories according to the selection made by the setting circuit. The first mode is a mode in which each of the sub-pixels is coupled to one of the at least one memory included in the sub-pixel, and the second mode is a mode including a time period in which at least one of the sub-pixels is coupled to the at least one memory included in another of the sub-pixels.

公开(公告)号：US20200349899A1

公开(公告)日：2020-11-05

申请号：US16932306

申请日：2020-07-17

Applicant: Japan Display Inc.

Inventor： Masashi Mitsui ,  Susumu Kimura ,  Yutaka Mitsuzawa

IPC: G09G3/36

Abstract: According to an aspect, a display device includes: sub-pixels arranged in row and column directions and each including a memory block including memories to store therein sub-pixel data; memory selection line groups corresponding to rows and each including memory selection lines electrically coupled to the memory blocks in the respective sub-pixels that belong to the corresponding row; and a memory selection circuit configured to concurrently output a memory selection signal to the memory selection line groups. Each sub-pixel displays an image based on the sub-pixel data stored in one of the memories in accordance with the memory selection line supplied with the memory selection signal. The number of times that the set value is changed is less than the number of times that images are switched from one to another based on the memory selection signal output from the memory selection circuit.

公开(公告)号：US20190197996A1

公开(公告)日：2019-06-27

申请号：US16227067

申请日：2018-12-20

Applicant: Japan Display Inc.

Inventor： Yutaka Mitsuzawa

IPC: G09G5/399

CPC classification number: G09G5/399 ,  G09G2360/12

Abstract: A display device includes: a display area including partial display areas; sub-pixels, each sub-pixel including a memory block with memories to store sub-pixel data; memory selection line groups, each of which is provided in each row or column in each partial display area and includes memory selection lines, each memory selection line electrically being coupled to the memory blocks, each of which belongs to the sub-pixels arranged in the row or the column; a memory selection control circuit for one of the memory selection lines from each memory selection line group, the memory selection lines selected functioning as an output destination of a memory selection signal for selecting one of the memories in the memory block; a memory selection circuit outputting the memory selection signal; and distribution circuits outputting the memory selection signal to the selected one of the memory selection lines in each memory selection line group.

公开(公告)号：US11521571B2

公开(公告)日：2022-12-06

申请号：US17480754

申请日：2021-09-21

Applicant: Japan Display Inc.

Inventor： Yutaka Mitsuzawa ,  Tatsuya Ishii

IPC: G09G3/36 ,  G09G3/00

Abstract: According to one embodiment, a display device including a plurality of pixels each of which includes a memory is provided. The display device includes a plurality of signal lines connected to the plurality of pixels, a signal line drive circuit configured to provide a data signal to one of the memories through one of the signal lines, a readout circuit configured to read the data signal in the memory through the signal line, and an output wire configured to externally output the data signal read by the readout circuit without passing through the signal line drive circuit.

公开(公告)号：US10997933B2

公开(公告)日：2021-05-04

申请号：US16744638

申请日：2020-01-16

Applicant: Japan Display Inc.

Inventor： Yutaka Mitsuzawa ,  Takayuki Nakao ,  Yutaka Ozawa ,  Masaya Tamaki

IPC: G09G3/36 ,  H04N5/3745 ,  G09G5/39 ,  G11C11/16 ,  G11C11/14

Abstract: A display device is provided and includes sub-pixels each including a sub-pixel electrode, and a first and second memory; a clock signal output circuit configured to, based on a reference clock signal, output a plurality of clock signals having different frequencies; a selection circuit configured to select one of the clock signals as a selected clock signal; a memory selection circuit configured to select all of the first memories included in all the sub-pixels or all of the second memories included in all the sub-pixels in synchronization with the selected clock signal; a common electrode facing all of the sub-pixel electrodes; and a common-electrode driving circuit configured to provide a common potential to the common electrode, wherein the common potential is inverted in synchronization with the reference clock signal, wherein the sub-pixel electrode is driven based on sub-pixel data stored in the selected one of the memories to display an image.