公开(公告)号：US08357942B2

公开(公告)日：2013-01-22

申请号：US12296624

申请日：2007-10-01

Applicant: Kazutaka Takagi

Inventor： Kazutaka Takagi

IPC: H01L29/12

CPC classification number: H01L23/36 ,  H01G4/33 ,  H01G4/40 ,  H01L23/49805 ,  H01L23/50 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L25/16 ,  H01L2224/48091 ,  H01L2224/48195 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: In a semiconductor device by which peripheral circuit sections, such as a semiconductor element, a matching circuit section, a bias circuit section, a capacitor element, are placed on and connected to a substrate, the semiconductor element can be grounded, and the semiconductor device which can make heat radiation characteristics of the semiconductor element satisfactory is provided, without providing a via hole into a semiconductor substrate.It includes: a semiconductor element (2) placed on a substrate (1); peripheral circuit sections (30) and (40) placed on the substrate (1) and connected with the semiconductor element (2); an electrode (30e) provided in the peripheral circuit section (30) and grounded; an electrode (30s) for grounding connected to a metal layer (30m), a metal layer (30m) and a source electrode (2s) of the semiconductor element (2); and an electrode (30d) connected to a gate electrode (2g) of the semiconductor element (2).

Abstract translation: 在将半导体元件，匹配电路部分，偏置电路部分，电容器元件等外围电路部分放置在衬底上并连接到衬底的半导体器件中，半导体元件可以接地，半导体器件 可以提供半导体元件的散热特性，而不在半导体基板中设置通路孔。 它包括：放置在基板（1）上的半导体元件（2）; 外围电路部分（30）和（40）放置在基板（1）上并与半导体元件（2）连接; 设置在外围电路部分（30）中并接地的电极（30e） 用于接地连接到金属层（30m）的电极（30s），半导体元件（2）的金属层（30m）和源电极（2s）; 以及与半导体元件（2）的栅电极（2g）连接的电极（30d）。

公开(公告)号：US07990223B1

公开(公告)日：2011-08-02

申请号：US12976207

申请日：2010-12-22

Applicant: Kazutaka Takagi

Inventor： Kazutaka Takagi

IPC: H03F3/14

CPC classification number: H03F3/195 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/42316 ,  H01L29/7786 ,  H01L29/812 ,  H01L2223/6644 ,  H01L2223/6655 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13063 ,  H01L2924/13091 ,  H01L2924/1461 ,  H03F1/523 ,  H03F1/56 ,  H03F2200/18 ,  H03F2200/222 ,  H03F2200/387 ,  H03F2200/447 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: According to one embodiment, provided is a high frequency module comprising: a semiconductor device; an input matching circuit; an output matching circuit; a high temperature operating use gate bias circuit and operating use gate bias circuit connected to the input matching circuit; a high temperature operating use gate bias terminal connected to the high temperature operating use gate bias circuit; an operating use gate bias terminal connected to the operating use gate bias circuit; a high frequency input terminal connected to the input matching circuit; a drain bias circuit connected to the output matching circuit; a drain bias terminal connected to the drain bias circuit; and a high frequency output terminal connected to the output matching circuit, wherein the high frequency module is housed by one package.

Abstract translation: 根据一个实施例，提供了一种高频模块，包括：半导体器件; 输入匹配电路; 输出匹配电路; 高温操作使用栅极偏置电路和操作使用栅极偏置电路连接到输入匹配电路; 高温操作使用栅极偏置端子连接到高温操作使用栅极偏置电路; 连接到操作使用栅极偏置电路的工作使用栅极偏置端子; 连接到输入匹配电路的高频输入端; 连接到输出匹配电路的漏极偏置电路; 漏极偏置端子，连接到漏极偏置电路; 以及连接到输出匹配电路的高频输出端子，其中高频模块由一个封装容纳。

公开(公告)号：US07888797B2

公开(公告)日：2011-02-15

申请号：US11367460

申请日：2006-03-06

Applicant: Kazutaka Takagi

Inventor： Kazutaka Takagi

IPC: H01L23/043 ,  H01L23/10

CPC classification number: H01L23/047 ,  H01L23/66 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/1616 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A lid forms an internal space on a bottom plate together with a plurality of side walls. A dielectric plate on the bottom plate in the internal space has a smaller width than an inner surface of the lid. A projection on the inner surface of the lid has a surface area, where a distance between the projection and the bottom plate where the projection is provided is shorter than a distance between the lid and the bottom plate where the projection is not provided. The lid and the projection are coupled to pass a current therebetween. The inner surface of the lid extends further toward an inner surface of one of the side walls than does the projection. The bottom plate, the side walls, the lid, and the projection are composed of metal material. The lid and the projection are composed of the same metal material.

Abstract translation: 盖子与多个侧壁一起形成在底板上的内部空间。 内部空间的底板上的电介质板的宽度比盖的内表面宽。 在盖的内表面上的突起具有表面区域，其中突起和设置有突起的底板之间的距离比盖子和未设置突起的底板之间的距离短。 盖和突起被联接以在其间传递电流。 盖的内表面比突出部分进一步朝向一个侧壁的内表面延伸。 底板，侧壁，盖和突起由金属材料构成。 盖和突起由相同的金属材料组成。

公开(公告)号：US20100073099A1

公开(公告)日：2010-03-25

申请号：US12417089

申请日：2009-04-02

Applicant: Choon Yong NG ,  Kazutaka Takagi ,  Naotaka Tomita

Inventor： Choon Yong NG ,  Kazutaka Takagi ,  Naotaka Tomita

IPC: H03B9/12

CPC classification number: H03F3/245 ,  H03F1/086 ,  H03F3/195 ,  H03F2200/391 ,  H03F2200/451

Abstract: A stabilization network and a semiconductor device having the stabilization network wherein the stabilization network includes an active element having a negative resistance accompanying a high frequency negative resistance oscillation; and a tank circuit composed of a resistance connected to a main electrode of the active element, an inductance and capacitance which are connected in parallel with the resistance and synchronize with an oscillating frequency of the high frequency negative resistance oscillation, wherein the stabilization network is performed for suppressing a negative resistance accompanying a Gunn oscillation and obtaining stable and highly efficient power amplification.

Abstract translation: 一种稳定网络和具有稳定网络的半导体器件，其中稳定网络包括具有伴随高频负电阻振荡的负电阻的有源元件; 以及由与有源元件的主电极连接的电阻构成的振荡电路，与电阻并联连接并与高频负电阻振荡的振荡频率同步的电感和电容，其中执行稳定网络 用于抑制伴随Gunn振荡的负电阻并获得稳定和高效的功率放大。

公开(公告)号：US07659613B2

公开(公告)日：2010-02-09

申请号：US12137611

申请日：2008-06-12

Applicant: Kazutaka Takagi

Inventor： Kazutaka Takagi

IPC: H01L23/04

CPC classification number: H01L23/50 ,  H01L23/047 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/4911 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/16195 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A frame-shaped sidewall is provided on a metallic base plate surrounding a semiconductor element arranged on the metallic base plate, which is provided with a stepped surface positioned at lower level at a portion of the base plate than a main surface of the base plate. A first dielectric plate is arranged on one side of the semiconductor element and a first circuit pattern is formed on its surface, a second dielectric plate is arranged on another side of the semiconductor element and a second circuit pattern is formed on the first and the second dielectric plate. An insulator is mounted on the stepped surface of the base plate, which forms a part of the sidewall. Power supply portions are provided including a band-shaped conductor. An interconnection is provided which connects the band-shaped conductor to the circuit pattern.

Abstract translation: 框架状的侧壁设置在金属基板上，该金属基板围绕设置在金属基板上的半导体元件，该半导体元件在底板的一部分处设置有比基板的主表面更低位置的阶梯表面。 第一电介质板被布置在半导体元件的一侧上，并且在其表面上形成第一电路图案，第二电介质板被布置在半导体元件的另一侧上，并且第二电路图案形成在第一和第二 电介质板。 绝缘体安装在形成侧壁的一部分的基板的台阶表面上。 提供包括带状导体的电源部分。 提供将带状导体连接到电路图案的互连。

公开(公告)号：US07486157B2

公开(公告)日：2009-02-03

申请号：US11509764

申请日：2006-08-25

Applicant: Kazutaka Takagi

Inventor： Kazutaka Takagi

IPC: H03H7/38

CPC classification number: H01L23/66 ,  H01L23/552 ,  H01L24/49 ,  H01L2223/6627 ,  H01L2224/45014 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/1903 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/3025 ,  H01P5/02 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In an embodiment of the invention, a package for high frequency waves mounted by a high frequency electronic circuit comprises an hermetic box-shaped high frequency package containing a high frequency electronic circuit in the inside and shielded by a conductor, an input terminal and an output terminal partly led out to the outside of the high frequency package, an input side feed-through section having one of its opposite ends connected to the input terminal and the other end connected to the high frequency electronic circuit and having a predetermined characteristic impedance; and an output side feed-through section having one of its opposite ends connected to the output terminal and the other end connected to the high frequency electronic circuit and having a characteristic impedance lower than the characteristic impedance of the input side feed-through section as viewed from the output terminal side.

Abstract translation: 在本发明的一个实施例中，由高频电子电路安装的用于高频波的封装包括在内部包含高频电子电路并由导体屏蔽的密封盒形高频封装，输入端子和输出端 端子部分引导到高频封装的外部，输入侧馈通部分，其相对端中的一端连接到输入端子，另一端连接到高频电子电路并具有预定的特性阻抗; 以及输出侧馈通部分，其相对端中的一端连接到输出端子，另一端连接到高频电子电路，并具有比所观察到的输入侧馈通部分的特性阻抗低的特性阻抗 从输出端子侧。

公开(公告)号：US20080246141A1

公开(公告)日：2008-10-09

申请号：US12137611

申请日：2008-06-12

Applicant: Kazutaka Takagi

Inventor： Kazutaka Takagi

IPC: H01L23/48

CPC classification number: H01L23/50 ,  H01L23/047 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/4911 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/16195 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A frame-shaped sidewall is provided on a metallic base plate surrounding a semiconductor element arranged on the metallic base plate, which is provided with a stepped surface positioned at lower level at a portion of the base plate than a main surface of the base plate. A first dielectric plate is arranged on one side of the semiconductor element and a first circuit pattern is formed on its surface, a second dielectric plate is arranged on another side of the semiconductor element and a second circuit pattern is formed on the first and the second dielectric plate. An insulator is mounted on the stepped surface of the base plate, which forms a part of the sidewall. Power supply portions are provided including a band-shaped conductor. An interconnection is provided which connects the band-shaped conductor to the circuit pattern.

Abstract translation: 框架状的侧壁设置在金属基板上，该金属基板围绕设置在金属基板上的半导体元件，该半导体元件在底板的一部分处设置有比基板的主表面更低位置的阶梯表面。 第一电介质板被布置在半导体元件的一侧上，并且在其表面上形成第一电路图案，第二电介质板被布置在半导体元件的另一侧上，并且第二电路图案形成在第一和第二 电介质板。 绝缘体安装在形成侧壁的一部分的基板的台阶表面上。 提供包括带状导体的电源部分。 提供将带状导体连接到电路图案的互连。

公开(公告)号：US20080246140A1

公开(公告)日：2008-10-09

申请号：US12137620

申请日：2008-06-12

Applicant: Kazutaka Takagi

Inventor： Kazutaka Takagi

IPC: H01L23/04 ,  H05K1/18

CPC classification number: H01L23/50 ,  H01L23/047 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/4911 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/16195 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A frame-shaped sidewall is provided on a metallic base plate surrounding a semiconductor element arranged on the metallic base plate, a first dielectric plate is arranged on one side of the semiconductor element and a first circuit pattern is formed on its surface, a second dielectric plate is arranged on another side of the semiconductor element and a second circuit pattern is formed and the first and the second dielectric plate. Power supply portions are provided on a part of the sidewall, through which a first or a second band-shaped conductors is penetrating. A relay post is provided on the dielectric plate. The first band-shaped conductor is connected to the circuit pattern by an interconnection via the relay post.

Abstract translation: 在围绕设置在金属基板上的半导体元件的金属基板上设置框状侧壁，第一电介质板设置在半导体元件的一侧，第一电路图案形成在其表面上，第二电介质 板被布置在半导体元件的另一侧上，并且形成第二电路图案和第一和第二电介质板。 电源部设置在侧壁的一部分上，第一或第二带状导体穿过该部分。 在电介质板上设置有继电器柱。 第一带状导体经由继电器柱连接到电路图案。

公开(公告)号：US20070080763A1

公开(公告)日：2007-04-12

申请号：US11509764

申请日：2006-08-25

Applicant: Kazutaka Takagi

Inventor： Kazutaka Takagi

IPC: H01P1/00

CPC classification number: H01L23/66 ,  H01L23/552 ,  H01L24/49 ,  H01L2223/6627 ,  H01L2224/45014 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/1903 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/3025 ,  H01P5/02 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In an embodiment of the invention, a package for high frequency waves mounted by a high frequency electronic circuit comprises an hermetic box-shaped high frequency package containing a high frequency electronic circuit in the inside and shielded by a conductor, an input terminal and an output terminal partly led out to the outside of the high frequency package, an input side feed-through section having one of its opposite ends connected to the input terminal and the other end connected to the high frequency electronic circuit and having a predetermined characteristic impedance; and an output side feed-through section having one of its opposite ends connected to the output terminal and the other end connected to the high frequency electronic circuit and having a characteristic impedance lower than the characteristic impedance of the input side feed-through section as viewed from the output terminal side.

Abstract translation: 在本发明的一个实施例中，由高频电子电路安装的用于高频波的封装包括在内部包含高频电子电路并由导体屏蔽的密封盒形高频封装，输入端子和输出端 端子部分引导到高频封装的外部，输入侧馈通部分，其相对端中的一端连接到输入端子，另一端连接到高频电子电路并具有预定的特性阻抗; 以及输出侧馈通部分，其相对端中的一端连接到输出端子，另一端连接到高频电子电路，并具有比所观察到的输入侧馈通部分的特性阻抗低的特性阻抗 从输出端子侧。

公开(公告)号：US09035702B2

公开(公告)日：2015-05-19

申请号：US13728167

申请日：2012-12-27

Applicant: Kazutaka Takagi

Inventor： Kazutaka Takagi

IPC: H03F3/04 ,  H03F1/56 ,  H03F3/60 ,  H01L23/64 ,  H01L23/66

CPC classification number: H03F3/04 ,  H01L23/64 ,  H01L23/66 ,  H01L2223/6655 ,  H01L2224/48137 ,  H01L2224/49175 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H03F1/565 ,  H03F3/60 ,  H03F2200/222 ,  H03F2200/387 ,  H03F2200/423 ,  H01L2924/00

Abstract: A microwave semiconductor amplifier includes a semiconductor amplifier element, an input matching circuit and an output matching circuit. The semiconductor amplifying element includes an input electrode and an output electrode and has a capacitive output impedance. The input matching circuit is connected to the input electrode. The output matching circuit includes a bonding wire and a first transmission line. The bonding wire includes first and second end portions. The first end portion is connected to the output electrode. The second end portion is connected to one end portion of the first transmission line. A fundamental impedance and a second harmonic impedance seen toward the external load change toward the one end portion. The second harmonic impedance at the one end portion has an inductive reactance. The output matching circuit matches the capacitive output impedance of the semiconductor amplifying element to the fundamental impedance of the external load.

Abstract translation: 微波半导体放大器包括半导体放大器元件，输入匹配电路和输出匹配电路。 半导体放大元件包括输入电极和输出电极，并且具有电容性输出阻抗。 输入匹配电路连接到输入电极。 输出匹配电路包括接合线和第一传输线。 接合线包括第一端部和第二端部。 第一端部连接到输出电极。 第二端部连接到第一传输线的一个端部。 朝向外部负载看到的基本阻抗和二次谐波阻抗向着一端部变化。 一端部的二次谐波阻抗具有感抗。 输出匹配电路将半导体放大元件的电容输出阻抗与外部负载的基波阻抗匹配。