公开(公告)号：US20140052956A1

公开(公告)日：2014-02-20

申请号：US13969562

申请日：2013-08-17

Applicant: Laurent MOLL

Inventor： Laurent MOLL

IPC: G06F12/02

CPC classification number: G06F12/1036 ,  G06F12/0207 ,  G06F12/0215 ,  G06F12/0811 ,  G06F12/1027 ,  G06F12/1081 ,  G06F17/5009 ,  G06F2212/681

Abstract: A multi-dimension engine, connected to a system TLB, generates sequences of addresses to request page address translation prefetch requests in advance of predictable accesses to elements within data arrays. Prefetch requests are filtered to avoid redundant requests of translations to the same page. Prefetch requests run ahead of data accesses but are tethered to within a reasonable range. The number of pending prefetches are limited. A system TLB stores a number of translations, the number being relative to the dimensions of the range of elements accessed from within the data array.

Abstract translation: 连接到系统TLB的多维引擎在对数据阵列内的元素的可预测访问之前产生地址序列以请求页面地址转换预取请求。 预取提取请求被过滤以避免翻译到同一页面的冗余请求。 预取请求在数据访问之前运行，但系在一个合理的范围内。 待处理的预取数量有限。 系统TLB存储多个翻译，该数字相对于从数据阵列内访问的元素的范围的维数而言。

公开(公告)号：US20140052919A1

公开(公告)日：2014-02-20

申请号：US13969451

申请日：2013-08-16

Applicant: Laurent MOLL ,  Jean-Jacques LECLER ,  Philippe BOUCARD

Inventor： Laurent MOLL ,  Jean-Jacques LECLER ,  Philippe BOUCARD

IPC: G06F12/10 ,  G06F17/50 ,  G06F12/08

CPC classification number: G06F12/1036 ,  G06F12/0207 ,  G06F12/0215 ,  G06F12/0811 ,  G06F12/1027 ,  G06F12/1081 ,  G06F17/5009 ,  G06F2212/681

Abstract: System TLBs are integrated within an interconnect, use a and share a transport network to connect to a shared walker port. Transactions are able to pass STLB allocation information through a second initiator side interconnect, in a way that interconnects can be cascaded, so as to allow initiators to control a shared STLB within the first interconnect. Within the first interconnect, multiple STLBs share an intermediate-level translation cache that improves performance when there is locality between requests to the two STLBs.

Abstract translation: 系统TLB集成在互连中，使用并共享传输网络连接到共享步进端口。 事务能够通过第二发起方侧互连传递STLB分配信息，其中互连可以级联，以便允许发起者控制第一互连中的共享STLB。 在第一个互连中，多个STLB共享中间级转换缓存，当在两个STLB的请求之间存在局部性时，可提高性能。

公开(公告)号：US20140052954A1

公开(公告)日：2014-02-20

申请号：US13969425

申请日：2013-08-16

Applicant: Laurent MOLL ,  Jean-Jacques LECLER ,  Philippe BOUCARD

Inventor： Laurent MOLL ,  Jean-Jacques LECLER ,  Philippe BOUCARD

IPC: G06F12/02 ,  G06F12/10

CPC classification number: G06F12/1036 ,  G06F12/0207 ,  G06F12/0215 ,  G06F12/0811 ,  G06F12/1027 ,  G06F12/1081 ,  G06F17/5009 ,  G06F2212/681

Abstract: A system TLB accepts translation prefetch requests from initiators. Misses generate external translation requests to a walker port. Attributes of the request such as ID, address, and class, as well as the state of the TLB affect the allocation policy of translations within multiple levels of translation tables. Translation tables are implemented with SRAM, and organized in groups.

Abstract translation: 系统TLB接受来自发起者的翻译预取请求。 Misses会向Walker端口生成外部翻译请求。 诸如ID，地址和类的请求的属性以及TLB的状态会影响多级翻译表中的翻译分配策略。 翻译表用SRAM实现，并组织成组。

公开(公告)号：US20070186057A1

公开(公告)日：2007-08-09

申请号：US11559069

申请日：2006-11-13

Applicant: Laurent MOLL ,  Yu CHENG ,  Peter GLASKOWSKY ,  Seungyoon SONG

Inventor： Laurent MOLL ,  Yu CHENG ,  Peter GLASKOWSKY ,  Seungyoon SONG

IPC: G06F13/28

CPC classification number: G06F12/0835 ,  G06F1/3225 ,  G06F12/0802 ,  G06F12/0808 ,  G06F12/0864 ,  G06F12/0888 ,  G06F2212/1028 ,  G06F2212/6046 ,  Y02D10/13

Abstract: Small and power-efficient buffer/mini-cache sources and sinks selected DMA accesses directed to a memory space included in a coherency domain of a microprocessor when cached data in the microprocessor is inaccessible due to any or all of the microprocessor being in a low-power state not supporting snooping. Satisfying the selected DMA accesses via the buffer/mini-cache enables reduced power consumption by allowing the microprocessor (or portion thereof) to remain in the low-power state. The buffer/mini-cache may be operated (temporarily) incoherently with respect to the cached data in the microprocessor and flushed before deactivation to synchronize with the cached data when the microprocessor (or portion thereof) transitions to a high-power state that enables snooping. Alternatively the buffer/mini-cache may be operated in a manner (incrementally) coherent with the cached data. The microprocessor implements one or more processors having associated cache systems (such as various arrangements of first-, second-, and higher-level caches).

Abstract translation: 当微处理器中的缓存数据由于任何或所有微处理器处于低电平状态时，微处理器中的高速缓存数据不可访问时，小型和功率高效的缓冲器/微型高速缓冲存储器源和接收器被选择指向微处理器的相干域中的存储器空间， 电源状态不支持窥探。 通过缓冲器/微型缓存来满足所选择的DMA访问通过允许微处理器（或其一部分）保持在低功率状态来降低功耗。 缓冲器/微型高速缓存可以相对于微处理器中的高速缓存数据非相干地操作（暂时地），并且在微处理器（或其部分）转换到启用窥探的高功率状态之前，在去激活之前刷新以与缓存数据同步 。 或者，缓冲器/微型缓存可以以与缓存的数据相一致的方式（递增地）操作。 微处理器实现具有相关联的高速缓存系统（例如第一，第二和更高级别高速缓存的各种布置）的一个或多个处理器。

公开(公告)号：US20140095808A1

公开(公告)日：2014-04-03

申请号：US13938675

申请日：2013-07-10

Applicant: Laurent MOLL ,  Jean-Jacques LECLER

Inventor： Laurent MOLL ,  Jean-Jacques LECLER

IPC: G06F12/08

CPC classification number: G06F12/0831 ,  G06F12/0833

Abstract: A coherency controller, such as one used within a system-on-chip, is capable of issuing different types of snoops to coherent caches. The coherency controller chooses the type of snoop based on the type of request that caused the snoops or the state of the system or both. By so doing, coherent caches provide data when they have sufficient throughput, and are not required to provide data when they do not have insufficient throughput.

公开(公告)号：US20140095807A1

公开(公告)日：2014-04-03

申请号：US13938651

申请日：2013-07-10

Applicant: Laurent MOLL ,  Jean-Jacques Lecler

Inventor： Laurent MOLL ,  Jean-Jacques Lecler

IPC: G06F12/08

CPC classification number: G06F12/0831 ,  G06F12/0833

Abstract: A coherency controller, such as one used within a system-on-chip, is capable of issuing different types of snoops to coherent caches. The coherency controller chooses the type of snoop based on the type of request that caused the snoops or the state of the system or both. By so doing, coherent caches provide data when they have sufficient throughput, and are not required to provide data when they do not have insufficient throughput.

Abstract translation: 一个一致性控制器（例如在片上系统中使用的控制器）能够向相干缓存发出不同类型的监听。 一致性控制器根据引起窥探或系统状态或两者的请求的类型选择窥探的类型。 通过这样做，一致的高速缓存在它们具有足够的吞吐量时提供数据，并且当它们没有足够的吞吐量时不需要提供数据。

公开(公告)号：US20140052955A1

公开(公告)日：2014-02-20

申请号：US13969559

申请日：2013-08-17

Applicant: Laurent MOLL ,  Jean-Jacques LECLER ,  Philippe BOUCARD

Inventor： Laurent MOLL ,  Jean-Jacques LECLER ,  Philippe BOUCARD

IPC: G06F12/02

CPC classification number: G06F12/1036 ,  G06F12/0207 ,  G06F12/0215 ,  G06F12/0811 ,  G06F12/1027 ,  G06F12/1081 ,  G06F17/5009 ,  G06F2212/681

Abstract: A system with a prefetch address generator coupled to a system translation look-aside buffer that comprises a translation cache. Prefetch requests are sent for page address translations for predicted future normal requests. Prefetch requests are filtered to only be issued for address translations that are unlikely to be in the translation cache. Pending prefetch requests are limited to a configurable or programmable number. Such a system is simulated from a hardware description language representation.

Abstract translation: 具有预取地址发生器的系统，其耦合到包括翻译高速缓存的系统转换后备缓冲器。 发送预取请求以进行页面地址转换，以便将来预测未来的正常请求。 预取请求被过滤，只能发布用于不太可能在翻译缓存中的地址转换。 待处理的预取请求仅限于可配置或可编程的数字。 这种系统是从硬件描述语言表示模拟的。