DEVICE AND METHODS FOR MANAGING THE DATA INTEGRITY OF READ AND WRITE OPERATIONS

    公开(公告)号:US20240248794A1

    公开(公告)日:2024-07-25

    申请号:US18582524

    申请日:2024-02-20

    Applicant: Lemon Inc.

    CPC classification number: G06F11/1004 G06F11/1068

    Abstract: A computing device for verifying data integrity is provided, comprising a memory controller configured to receive a plurality of original data blocks. Each original data block has an associated initial CRC value. The memory controller then segments and recombines the received data blocks into logic blocks, and calculates a new logic block CRC value for each logic block. The logic blocks are transmitted with their respective new logic block CRC values to a storage device, and the logic blocks are written to non-volatile memory of the storage device in a write operation. After the write operation, a combined CRC value is calculated for the logic blocks and a combined CRC value for the original data blocks, and compare the combined CRC values. The memory controller determines whether the combined CRC values match. When they match, the memory controller generates a verification response verifying the integrity of the write operation.

    TECHNIQUES FOR CONTROLLING SIMULATION FOR HARDWARE OFFLOADING SYSTEMS

    公开(公告)号:US20240020178A1

    公开(公告)日:2024-01-18

    申请号:US18476004

    申请日:2023-09-27

    CPC classification number: G06F9/5083

    Abstract: Described are examples for simulating performance of a hardware offloading system including receiving, by a simulator that corresponds to a simulated architecture representing the hardware offloading system, input data from a user application for processing by the simulated architecture, preparing, by the simulator, corresponding output data for the input data without computing the corresponding output data by the simulated architecture, and returning, by the simulator, the corresponding output data to the user application after a simulated idle time related to computing the corresponding output data by the simulated architecture.

    DATA PROCESSING METHOD, DEVICE, COMPUTER APPARATUS AND STRORAGE MEDIUM

    公开(公告)号:US20250013567A1

    公开(公告)日:2025-01-09

    申请号:US18741900

    申请日:2024-06-13

    Abstract: The present disclosure provides a data processing method, a device, a computer apparatus and a storage medium, wherein the method includes: in response to a target disk receiving at least one write request within a preset time period, determining a size threshold value for classifying a data update type according to a size of write data respectively indicated by each write request; determining a data update type corresponding to each write request according to a size of each write request and the size threshold value; dividing write data of the write request to obtain a data block according to a preset data block size, and caching the data block in a cache region of the target disk corresponding to the data update type, the target disk has multiple types of cache regions configured therein, different cache regions are configured to support caching of data with different update frequencies.

    METHOD AND SYSTEM FOR ACCELERATION OR OFFLOADING UTILIZING A UNIFIED DATA POINTER

    公开(公告)号:US20240036940A1

    公开(公告)日:2024-02-01

    申请号:US18485418

    申请日:2023-10-12

    CPC classification number: G06F9/5083 G06F9/5027 G06F2209/509

    Abstract: Methods, systems, and devices for performing an acceleration process by offloading an operation. The system includes a hardware offloading engine that includes a hardware accelerator for performing the acceleration process. The hardware accelerator has a processor configured to receive a hardware offloading command, the hardware offloading command including an operation code, an input pointer, and an output pointer, in which at least one of the input pointer or the output pointer includes a unified data pointer that includes one or more bits of memory for identifying the source location for the input data or the destination location of the output data, parse the operation code, the input pointer, and the output pointer from the hardware offloading command, retrieve the input data based on the input pointer, and execute an offloaded operation on the input data based on the operation code.

    METHOD AND SYSTEM FOR ACCELERATION OR OFFLOADING UTILIZING A MULTIPLE INPUT DATA STREAM

    公开(公告)号:US20230409226A1

    公开(公告)日:2023-12-21

    申请号:US18461989

    申请日:2023-09-06

    CPC classification number: G06F3/0647 G06F3/067 G06F3/0604

    Abstract: Methods and systems for performing a hardware acceleration process that includes a hardware offloading engine. The hardware offloading engine includes an interface for communicating with a host device and a hardware accelerator for performing the acceleration process. The hardware accelerator has a processor configured to: receive from the interface a hardware offloading command from the host device, the hardware offloading command including an operation code, an input pointer, a total input size, and a first input size, parse the operation code, the input pointer, the total input size, and the first input size from the hardware offloading command, retrieve input data based on the input pointer and the total input size, separate the input data into a first data stream and a second data stream based on the first input size, and execute an offloaded operation on the first data stream and the second data stream.

    MULTI-DIMENSIONAL SOLID STATE DRIVE BLOCK ACCESS

    公开(公告)号:US20230195345A1

    公开(公告)日:2023-06-22

    申请号:US18108351

    申请日:2023-02-10

    Applicant: Lemon Inc.

    CPC classification number: G06F3/064 G06F3/0604 G06F3/0655 G06F3/0679

    Abstract: A method for accessing blocks of a solid state drive is described. A starting position is received, where the starting position identifies a first block of a contiguous block region within a namespace of the solid state drive. The contiguous block region is to be accessed according to a single input/output operation and the namespace comprises two dimensions of logical address space with respective indices for indexing blocks within a corresponding dimension of the logical address space. A first dimensional identifier that identifies a size of the contiguous block region in a first dimension of the namespace is received. A second dimensional identifier that identifies a size of the contiguous block region in a second dimension of the namespace is received. Blocks of the contiguous block region are accessed in response to the single input/output operation according to the starting position, the first dimensional identifier, and the second dimensional identifier.

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