Small, adaptable, real-time, scalable image processing chip
    1.
    发明授权
    Small, adaptable, real-time, scalable image processing chip 有权
    小型,适应性强,实时,可扩展的图像处理芯片

    公开(公告)号:US08869086B1

    公开(公告)日:2014-10-21

    申请号:US14067026

    申请日:2013-10-30

    CPC classification number: G06T1/20 G06F13/409

    Abstract: An imaging solution that uses a small, adaptable, real-time, scalable, image-processing (SMARTS IP) chip configured to function like any one of a wide range of specialized FPA imaging devices, and a method for configuring and implementing same is provided. Configuration for a wide range of applications and implementations, including ones with or without IDCA assemblies or other types of dewar/cooler structures, is disclosed. A wide range of output data formats, including all SDI-compatible image data formats, may be accomplished. Frame stacking and variable effective resolution and charge well depth levels may be accomplished in output image data based on on-chip image processing techniques. On-chip image processing algorithms may include XR™, DRC, NUC, and other similar or related techniques. Image data output compression through on-chip processing is also disclosed.

    Abstract translation: 提供了一种成像解决方案,其使用配置为像各种专业FPA成像设备中的任何一个一样工作的小型,适应性强,实时,可扩展的图像处理(SMARTS IP)芯片,以及配置和实现相同的方法 。 公开了用于各种应用和实现的配置,包括具有或不具有IDCA组件或其他类型的杜瓦瓶/冷却器结构的应用和实现。 可以实现各种输出数据格式,包括所有SDI兼容的图像数据格式。 可以在基于片上图像处理技术的输出图像数据中实现帧堆叠和可变有效分辨率和电荷阱深度级。 片上图像处理算法可以包括XR TM,DRC,NUC和其他相似或相关技术。 还公开了通过片上处理的图像数据输出压缩。

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