Novel gate dielectric structure for reducing boron penetration and current leakage
    1.
    发明申请
    Novel gate dielectric structure for reducing boron penetration and current leakage 失效
    用于减少硼渗透和电流泄漏的新型栅介质结构

    公开(公告)号:US20040238905A1

    公开(公告)日:2004-12-02

    申请号:US10847789

    申请日:2004-05-18

    CPC classification number: H01L21/28202 H01L29/513

    Abstract: The present invention provides a semiconductor device capable of substantially retarding boron penetration within the semiconductor device and a method of manufacture therefor. In the present invention the semiconductor device includes a gate dielectric located over a substrate of a semiconductor wafer, wherein the gate dielectric includes a nitrided layer and a dielectric layer. The present invention further includes a nitrided transition region located between the dielectric layer and the nitrided layer and a gate located over the gate dielectric.

    Abstract translation: 本发明提供一种能够显着延迟半导体器件内的硼渗透的半导体器件及其制造方法。 在本发明中,半导体器件包括位于半导体晶片的衬底之上的栅极电介质,其中栅极电介质包括氮化层和电介质层。 本发明还包括位于介电层和氮化层之间的氮化过渡区域和位于栅极电介质上方的栅极。

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