BUFFER CIRCUITS AND SEMICONDUCTOR STRUCTURES THEREOF

    公开(公告)号:US20250141446A1

    公开(公告)日:2025-05-01

    申请号:US19009332

    申请日:2025-01-03

    Applicant: MEDIATEK INC.

    Abstract: A buffer circuit is provided to output an output signal at an output node. The buffer circuit includes first and second inverters and first and second switches. The first inverter inverts an input signal. The second inverter is coupled between the first inverter and the output node. The first switch is coupled between a first voltage source terminal and the output node. The second switch is coupled between the output node and a second voltage source terminal. First and second voltages are respectively provided to the first and second voltage source terminals. In response to the input signal switching to a first level from a second level, the first switch is turned on to pre-charge the output node. In response to the input signal transiting to the second level from the first level, the second switch is turned on to pre-discharge the output node.

    BUFFER CIRCUITS AND SEMICONDUCTOR STRUCTURES THEREOF

    公开(公告)号:US20230308099A1

    公开(公告)日:2023-09-28

    申请号:US18183359

    申请日:2023-03-14

    Applicant: MEDIATEK INC.

    CPC classification number: H03K17/6872 H03K19/20 H01L27/0928

    Abstract: A buffer circuit is provided to output an output signal at an output node. The buffer circuit includes first and second inverters and first and second switches. The first inverter inverts an input signal. The second inverter is coupled between the first inverter and the output node. The first switch is coupled between a first voltage source terminal and the output node. The second switch is coupled between the output node and a second voltage source terminal. First and second voltages are respectively provided to the first and second voltage source terminals. In response to the input signal switching to a first level from a second level, the first switch is turned on to pre-charge the output node. In response to the input signal transiting to the second level from the first level, the second switch is turned on to pre-discharge the output node.

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