公开(公告)号：US20230178557A1

公开(公告)日：2023-06-08

申请号：US18050630

申请日：2022-10-28

Applicant: MEDIATEK INC.

Inventor： Ho-Chieh HSIEH ,  Kin-Hooi DIA ,  Hsing-I TSAI

IPC: H01L27/118 ,  H01L27/02

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L2027/11829 ,  H01L2027/11881

Abstract: A semiconductor structure is provided. A logic cell includes a first transistor in a first active region, a second gate electrode and a third gate electrode on opposite sides of the first transistor, a second transistor in a second active region, and a first isolation structure and a second isolation structure on opposite edges of the second active region. The first transistor includes a first gate electrode extending in a first direction. The second and third gate electrodes extend in the first direction, and the first and second isolation structures extend in the first direction. The second transistor and the first transistor share the first gate electrode. The first isolation structure is aligned with the second gate structure in the first direction, and the second isolation structure is aligned with the third gate structure in the first direction.

公开(公告)号：US20230178537A1

公开(公告)日：2023-06-08

申请号：US18051026

申请日：2022-10-31

Applicant: MEDIATEK INC.

Inventor： Kin-Hooi DIA ,  Ho-Chieh HSIEH ,  Hsing-I TSAI

IPC: H01L27/02 ,  H01L27/092

CPC classification number: H01L27/0207 ,  H01L27/092 ,  H01L21/76224

Abstract: A semiconductor structure is provided. The semiconductor structure includes a cell array having a plurality of rows. The cell array includes a plurality of first logic cells arranged in at least one first row, and a plurality of second logic cells arranged in at least one second row. The first logic cells share a first active region. Each of the second logic cells has a second active region, and the second active regions of two adjacent second logic cells are separated from each other by an isolation structure. The first logic cells of the first row are in contact with the second logic cells of the second row.