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公开(公告)号：US20250158769A1
公开(公告)日：2025-05-15
申请号：US18939453
申请日：2024-11-06
Applicant: MEDIATEK INC.
Inventor： Ming-Hsiang Tseng , Cheng-En Hsieh , Hao-Chih Yu , Tzu-Hao Yu
Abstract: A method for reducing sounding overhead by shortening TB-PPDU duration for trigger-based implicit feedback and associated apparatus are provided, where a non-AP STA device is wirelessly linking to an AP device, and a number of sounding dimension of the non-AP STA device is less than a maximum number of spatial streams of the AP device. The method may include: transmitting a first frame regarding TB-sounding as well as a trigger frame, with at least one field of at least one frame among the first frame and the trigger frame being set to shorten the TB-PPDU duration; and receiving a sounding feedback having the TB-PPDU duration to be the trigger-based implicit feedback, for use of generating a beamforming steering matrix for transmission beamforming, wherein the at least one field is set to shorten a time for receiving a useless part within the sounding feedback, for reducing the sounding overhead.
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2.发明授权公开(公告)号：US09094034B2
公开(公告)日：2015-07-28
申请号：US14483137
申请日：2014-09-10
Applicant: MEDIATEK INC.
Inventor： Sheng-Hao Chen , Yen-Chuan Huang , Min-Hua Wu , Chun-Hao Liao , Hung-Pin Ma , Tzu-Hao Yu , Jen-Che Tsai
CPC classification number: H03M1/0626 , H03M1/66 , H03M1/74 , H03M9/00
Abstract: A digital to analog converting system, which comprises: a first data converting circuit, for receiving a first digital data stream transmitted at a first clock frequency, for converting the first digital data stream to a plurality of second digital data streams transmitted at a second clock frequency, and for outputting the second digital data streams in parallel; a second data converting circuit, for receiving the second digital data streams from the first data converting circuit, and for converting the second digital data streams to a third digital data stream transmitted at a third clock frequency; and a first digital to analog converter, for converting the third digital data stream to a first output analog data stream. The second clock frequency is lower than the first clock frequency and the third clock frequency.
Abstract translation: 一种数模转换系统，包括：第一数据转换电路，用于接收以第一时钟频率发送的第一数字数据流，用于将第一数字数据流转换为在第二时钟发送的多个第二数字数据流 并且用于并行地输出第二数字数据流; 第二数据转换电路，用于从第一数据转换电路接收第二数字数据流，并将第二数字数据流转换成以第三时钟频率发送的第三数字数据流; 以及第一数模转换器，用于将第三数字数据流转换为第一输出模拟数据流。 第二个时钟频率低于第一个时钟频率和第三个时钟频率。
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3.发明申请公开(公告)号：US20150123830A1
公开(公告)日：2015-05-07
申请号：US14483137
申请日：2014-09-10
Applicant: MEDIATEK INC.
Inventor： Sheng-Hao Chen , Yen-Chuan Huang , Min-Hua Wu , Chun-Hao Liao , Hung-Pin Ma , Tzu-Hao Yu , Jen-Che Tsai
CPC classification number: H03M1/0626 , H03M1/66 , H03M1/74 , H03M9/00
Abstract: A digital to analog converting system, which comprises: a first data converting circuit, for receiving a first digital data stream transmitted at a first clock frequency, for converting the first digital data stream to a plurality of second digital data streams transmitted at a second clock frequency, and for outputting the second digital data streams in parallel; a second data converting circuit, for receiving the second digital data streams from the first data converting circuit, and for converting the second digital data streams to a third digital data stream transmitted at a third clock frequency; and a first digital to analog converter, for converting the third digital data stream to a first output analog data stream. The second clock frequency is lower than the first clock frequency and the third clock frequency.
Abstract translation: 一种数模转换系统，包括：第一数据转换电路，用于接收以第一时钟频率发送的第一数字数据流，用于将第一数字数据流转换为在第二时钟发送的多个第二数字数据流 并且用于并行地输出第二数字数据流; 第二数据转换电路，用于从第一数据转换电路接收第二数字数据流，并将第二数字数据流转换成以第三时钟频率发送的第三数字数据流; 以及第一数模转换器，用于将第三数字数据流转换为第一输出模拟数据流。 第二个时钟频率低于第一个时钟频率和第三个时钟频率。
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