公开(公告)号：US20230386954A1

公开(公告)日：2023-11-30

申请号：US18132437

申请日：2023-04-10

Applicant: MEDIATEK INC.

Inventor： Yu-Tung Chen ,  Pei-Haw Tsao ,  Kuo-Lung Fan

IPC: H01L23/31 ,  H01L21/683

CPC classification number: H01L23/3185 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2221/68377

Abstract: A wafer level chip scale package includes a bare silicon die having an active surface, a rear surface opposite to the active surface, and a sidewall surface between the active surface and the rear surface. The bare silicon die includes a backside corner between the rear surface and the sidewall surface. A plurality of pads is disposed on the active surface. A plurality of conductive elements is disposed on the plurality of pads, respectively. A backside tape is adhered to the rear surface by using an adhesive layer. The adhesive layer and the backside tape protrude beyond the sidewall surfaces of the bare silicon die. The adhesive layer extends along the sidewall surface and wraps around the backside corner.