公开(公告)号：US20240319782A1

公开(公告)日：2024-09-26

申请号：US18605933

申请日：2024-03-15

Applicant: MEDIATEK Inc.

Inventor： Tse-Chung LI ,  Tai-Ying JIANG ,  Ching-Wen CHEN ,  Shang-Wei CHEN

IPC: G06F1/3296 ,  G06F1/3209

CPC classification number: G06F1/3296 ,  G06F1/3209

Abstract: The processor comprises multiple sub-systems. Each sub-system is configured to generate a voltage switching signal. The processor also comprises a packetizing module coupled to the sub-systems. The packetizing module packetizes multiple voltage switching signals generated by the sub-systems to a packet. The processor also comprises a PMIF (power management interface) configured to receive the packet and output the packet.