公开(公告)号：US20230335192A1

公开(公告)日：2023-10-19

申请号：US17723673

申请日：2022-04-19

Applicant: Micron Technology, Inc.

Inventor： Vijayakrishna J. Vankayala ,  Hari Giduturi ,  Jason M. Brown

IPC: G11C13/00 ,  H01L25/065 ,  G11C11/16

CPC classification number: G11C13/0061 ,  H01L25/0657 ,  G11C11/1693 ,  H01L2225/06506 ,  H01L2225/06541

Abstract: A memory device includes a substrate with two or more memory die stacked in a three-dimensional stacked (3DS) configuration. The memory device includes a clock input configured to receive a clock from a host device. The memory device also includes a command input configured to receive command and address bits from the host device. The two or more memory die each include its own plurality of memory cells. Furthermore, each of the two or more memory die include a local control circuitry configured to receive or transmit a divided clock that is based on the clock.

公开(公告)号：US11380395B2

公开(公告)日：2022-07-05

申请号：US17013234

申请日：2020-09-04

Applicant: Micron Technology, Inc.

Inventor： Jason M. Brown ,  Vijayakrishna J. Vankayala

IPC: G11C13/00 ,  H03L7/081

Abstract: Memory devices may have a memory array and a delay locked loop (DLL) circuit that adjusts signals associated with operations to access of the memory array. The memory device may also include a controller that delays an access command to access the memory array by transmitting the access command through delay circuitry of the DLL circuit. This may cause the access command to be delayed by a first duration of time when output from the delay circuitry. Delay of the access command may align a data signal and the access command such that the access command and a system clock may cause latching of suitable data of the data signal.

公开(公告)号：US20220076745A1

公开(公告)日：2022-03-10

申请号：US17013234

申请日：2020-09-04

Applicant: Micron Technology, Inc.

Inventor： Jason M. Brown ,  Vijayakrishna J. Vankayala

IPC: G11C13/00 ,  H03L7/081

Abstract: Memory devices may have a memory array and a delay locked loop (DLL) circuit that adjusts signals associated with operations to access of the memory array. The memory device may also include a controller that delays an access command to access the memory array by transmitting the access command through delay circuitry of the DLL circuit. This may cause the access command to be delayed by a first duration of time when output from the delay circuitry. Delay of the access command may align a data signal and the access command such that the access command and a system clock may cause latching of suitable data of the data signal.

公开(公告)号：US20200294576A1

公开(公告)日：2020-09-17

申请号：US16886284

申请日：2020-05-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jason M. Brown ,  Daniel B. Penney

IPC: G11C11/406 ,  G11C16/34 ,  G11C7/10 ,  G06F11/30 ,  G11C11/4076

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for scheduling targeted refreshes in a memory device. Memory cells in a memory device may be volatile and may need to be periodically refreshed as part of an auto-refresh operation. In addition, certain rows may experience faster degradation, and may need to undergo targeted refresh operations, where a specific targeted refresh address is provided and refreshed. The rate at which targeted refresh operations need to occur may be based on the rate at which memory cells are accessed. The memory device may monitor accesses to a bank of the memory, and may use a count of the accesses to determine if an auto-refresh address or a targeted refresh address will be refreshed.

公开(公告)号：US11699476B2

公开(公告)日：2023-07-11

申请号：US17375817

申请日：2021-07-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jason M. Brown ,  Daniel B. Penney

IPC: G11C11/00 ,  G11C11/406 ,  G11C11/408

CPC classification number: G11C11/406 ,  G11C11/4087

Abstract: An apparatus may include multiple memory devices. Each memory device may include multiple memory banks. Addresses of accessed word lines for a particular portion of memory and the number of times those word lines are accessed may be tracked by each memory device. When a memory device determines that an accessed word line is an aggressor word line, the memory device alerts other memory devices of the apparatus. The memory devices may then perform targeted refresh operations on victim word lines of the aggressor word line.

公开(公告)号：US11532346B2

公开(公告)日：2022-12-20

申请号：US16886284

申请日：2020-05-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jason M. Brown ,  Daniel B. Penney

IPC: G11C11/40 ,  G11C11/406 ,  G11C16/34 ,  G11C7/10 ,  G06F11/30 ,  G11C11/4076 ,  G11C7/00

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for scheduling targeted refreshes in a memory device. Memory cells in a memory device may be volatile and may need to be periodically refreshed as part of an auto-refresh operation. In addition, certain rows may experience faster degradation, and may need to undergo targeted refresh operations, where a specific targeted refresh address is provided and refreshed. The rate at which targeted refresh operations need to occur may be based on the rate at which memory cells are accessed. The memory device may monitor accesses to a bank of the memory, and may use a count of the accesses to determine if an auto-refresh address or a targeted refresh address will be refreshed.

公开(公告)号：US20210407583A1

公开(公告)日：2021-12-30

申请号：US17470883

申请日：2021-09-09

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Jason M. Brown ,  Nathaniel J. Meier ,  Timothy B. Cowles ,  Jiyun Li

IPC: G11C11/406 ,  G11C11/408

Abstract: The address of victim rows may be determined based on rows that are accessed in a memory. The victim addresses may be stored and associated with a count for every time a victim row is “victimized.” When the count for a victim row reaches a threshold, the victim row may be refreshed to preserve data stored in the row. After the victim row has been refreshed, the count may be reset. When a victim row is accessed, the count may also be reset. The counts may be adjusted for closer victim rows (e.g., +/−1) at a faster rate than counts for more distant victim rows (e.g., +/−2). This may cause closer victim rows to be refreshed at a higher rate than more distant victim rows.

公开(公告)号：US20210343324A1

公开(公告)日：2021-11-04

申请号：US17375817

申请日：2021-07-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jason M. Brown ,  Daniel B. Penney

IPC: G11C11/406 ,  G11C11/408

Abstract: An apparatus may include multiple memory devices. Each memory device may include multiple memory banks. Addresses of accessed word lines for a particular portion of memory and the number of times those word lines are accessed may be tracked by each memory device. When a memory device determines that an accessed word line is an aggressor word line, the memory device alerts other memory devices of the apparatus. The memory devices may then perform targeted refresh operations on victim word lines of the aggressor word line.

公开(公告)号：US20210249058A1

公开(公告)日：2021-08-12

申请号：US17240921

申请日：2021-04-26

Applicant: Micron Technology, Inc.

Inventor： Jason M. Brown ,  Vijayakrishna J. Vankayala ,  Todd A. Dauenbaugh

IPC: G11C7/22

Abstract: A memory device includes a first data driver configured to send according to a first clock signal a first data to a first data port; a second data driver configured to send according to a second clock signal a second data to a second data port, wherein the second clock signal does not match the first clock signal.

公开(公告)号：US10534686B2

公开(公告)日：2020-01-14

申请号：US14168749

申请日：2014-01-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kallol Mazumder ,  Jason M. Brown ,  Derek R. May ,  Jeffrey E. Koelling ,  Roger D. Norwood

IPC: G06F11/34 ,  G11C11/408 ,  G11C11/406

Abstract: Apparatuses and methods for address detection are disclosed herein. An example apparatus includes an address filter and an address tracking circuit. The address filter may be configured to receive a first address and to determine whether the first address matches an address of a plurality of addresses associated with the address filter. The address tracking circuit may be coupled to the address filter and configured to store the first address responsive to a determination that the first address matches an address of the plurality of addresses associated with the address filter. The address tracking circuit may further be configured to receive a second address and to change a count associated with the first address based on the second address matching the first address. The address tracking circuit may be configured to selectively provide the first address responsive to the count.