公开(公告)号：US20210366528A1

公开(公告)日：2021-11-25

申请号：US17326352

申请日：2021-05-21

Applicant: MONTAGE TECHNOLOGY CO., LTD.

Inventor： Yi LI ,  Gang SHAN ,  Guohui LI ,  Chunhui ZHANG

IPC: G11C8/18 ,  G11C8/20 ,  G11C7/10

Abstract: The application discloses a memory controller coupled between a memory module and a host controller to control access of the host controller to the memory module, comprising a central buffer coupled between the host controller and the memory module. The central buffer is configured to receive a command/address signal from the host controller via a command/address channel and selectively provide the command/address signal to the memory module. The command/address signal has an identity authentication message for identifying a source. The central buffer comprises: a verification module coupled to the command/address channel to receive the command/address signal and the identity authentication message, and configured to determine whether the command/address signal conforms to an authority management rule based on the identity authentication message; and an access control module coupled to the command/address channel to receive the command/address signal and coupled to the verification module to receive the determination result, and configured to process the command/address signal based on the determination result to selectively provide the command/address signal to the memory module.

公开(公告)号：US20210303459A1

公开(公告)日：2021-09-30

申请号：US17107905

申请日：2020-11-30

Applicant: MONTAGE TECHNOLOGY CO., LTD.

Inventor： Stephen TAI ,  Yi LI

IPC: G06F12/02 ,  G06F12/14 ,  G06F13/16 ,  G06F13/42

Abstract: The application discloses a memory controller coupled between a memory module and a host controller to control accesses of the host controller to the memory module. The memory controller comprises a central buffer coupled between the memory module and the host controller via a command/address channel, wherein the central buffer is configured to receive a command/address signal from the host controller and provide the command/address signal to the memory module. The central buffer comprises: a recognition block coupled to the command/address channel to receive the command/address signal, wherein the recognition block is configured to generate access history information based on the received command/address signal; a compression block coupled to the recognition block to receive the access history information, wherein the compression block is configured to compress the access history information; and a transmission block, wherein the compressed access history information is transmitted out from the central buffer via the transmission block.

公开(公告)号：US20230185972A1

公开(公告)日：2023-06-15

申请号：US18060969

申请日：2022-12-02

Applicant: MONTAGE TECHNOLOGY CO., LTD.

Inventor： Yi LI

IPC: G06F21/85

CPC classification number: G06F21/85 ,  G06F2221/2141

Abstract: The present application relates to a control system with a security management device. The control system comprises: a bus; one or more electronic devices coupled to the bus to transmit data with the bus through respective communication protocols; one or more security monitoring managers each coupled between an electronic device and the bus, wherein each of the security monitoring managers is configured to snoop data transmitted between the electronic device and the bus based on a predetermined transmission protocol, determine whether the data conforms to a predetermined authority management rule to generate a determination result, and selectively allow the data to be transmitted to the bus or the electronic device according to the determination result, and wherein the predetermined transmission protocol correspond to the communication protocol of the electronic device; and a central security manager coupled to the security monitoring managers, wherein the central security manager is configured to configure the predetermined transmission protocol and the predetermined authority management rule used by each of the security monitoring managers.

公开(公告)号：US20220214974A1

公开(公告)日：2022-07-07

申请号：US17560204

申请日：2021-12-22

Applicant: MONTAGE TECHNOLOGY CO., LTD.

Inventor： Qiang LI ,  Yi LI ,  Liangliang NIU ,  Dongjie TANG ,  Yongjian LV

IPC: G06F12/10

Abstract: The present disclosure provides a method and apparatus for parsing contiguous system addresses, and an electronic device. The method for parsing contiguous system addresses comprises: acquiring system level information upon receiving contiguous system addresses; acquiring logical address ranges of objects in a first level based on the contiguous system addresses and the system level information; and when successively acquiring logical address ranges of objects in a second level, . . . , or an Nth level of the system, acquiring logical address ranges of objects in a present level based on a logical address range of a previous level and the system level information, wherein N is the number of levels, and N is an integer greater than or equal to 2, and a logical address range of an object comprises a start address and an end address of the object.

公开(公告)号：US20200371973A1

公开(公告)日：2020-11-26

申请号：US16881016

申请日：2020-05-22

Applicant: MONTAGE TECHNOLOGY CO., LTD.

Inventor： Gang SHAN ,  Yi LI ,  Howard Chonghe YANG

IPC: G06F13/16 ,  G06F13/42 ,  G06F13/38 ,  G06F11/10 ,  G06F21/78

Abstract: A data conversion control apparatus, comprising: at least one first interface each for coupling a first external interface, both of the first interface and the first external interface being in accordance with a predetermined physical interface standard, wherein data transmitted between the first interface and the first external interface is in accordance with a configurable application layer protocol; at least one second interface each for coupling a second external interface, wherein the second external interface is a memory interface in accordance with a predetermined memory interface standard, and the second interface is configurable to match the predetermined memory interface standard; and a data rebuild unit coupled between the at least one first interface and the at least one second interface, wherein the data rebuild unit is configured to rebuild data such that data can be transmitted in respective formats between the at least one first interface and the at least one second interface.

公开(公告)号：US20190205049A1

公开(公告)日：2019-07-04

申请号：US16239549

申请日：2019-01-04

Applicant: MONTAGE TECHNOLOGY CO., LTD.

Inventor： Gang SHAN ,  Howard Chonghe YANG ,  Yi LI

IPC: G06F3/06

CPC classification number: G06F3/0622 ,  G06F3/0629 ,  G06F3/0659 ,  G06F3/0673

Abstract: The application discloses a memory controller and a method for controlling an access to a memory module. The memory controller is coupled between the memory module and a host controller to control the access of the host controller to the memory module. The memory controller comprises: a central buffer coupled to the host controller for receiving data access command from the host controller and coupled to the memory module for providing an encrypted data access command to the memory module; wherein the central buffer comprises a command processing module, for performing encryption operation to a data access command with a predefined command encryption algorithm to generate an encrypted data access command; wherein a data channel is coupled between the memory module and the host controller, and wherein under the control of the encrypted data access command, the memory module exchanges data with the host controller via the data channel.

公开(公告)号：US20250086269A1

公开(公告)日：2025-03-13

申请号：US18826147

申请日：2024-09-05

Applicant: MONTAGE TECHNOLOGY CO., LTD.

Inventor： Liangliang NIU ,  Yi LI

IPC: G06F21/54 ,  G06F21/55 ,  G06F21/76

Abstract: A system and a method for managing a memory, and an electronic device are provided. The system comprises a memory allocator and a trusted driving module. The memory allocator receives a first memory access request for a target partition of the memory and obtains authentication information to generate an authentication request. The memory allocator manages one or more physical memory partitions of the memory, and the target partition is one of the physical memory partitions. The trusted driving module is configured to receive the authentication request, generate an authentication result, and return the authentication result to the memory allocator. The memory allocator is further configured to execute the first memory access request when the authentication result indicates that the authentication succeeds, and reject the first memory access request when the authentication result indicates that the authentication fails. The system of the present disclosure enhances the security of memory operating.

公开(公告)号：US20230081310A1

公开(公告)日：2023-03-16

申请号：US17891150

申请日：2022-08-19

Applicant: MONTAGE TECHNOLOGY CO., LTD.

Inventor： Yi LI

IPC: G06F3/06

Abstract: The application discloses a memory controller coupled between a memory module and a host controller to control access of the host controller to the memory module, the memory controller comprising: a central buffer coupled to the host controller via a command/address bus to receive a command/address signal from the host controller, wherein the central buffer is configured to determine whether the command/address signal conforms to an authority management rule and configure a buffer control command based on the determination result, so that the buffer control command indicates whether to restrict access of the host controller to the memory module; and a data buffer coupled via a data buffer command channel to the central buffer to receive the buffer control command, wherein the data buffer is configured to selectively restrict access of the host controller to the memory module based on the buffer control command; wherein the buffer control command comprises a plurality of time-sequenced fields, and the central buffer is configured to configure a second field or a field after the second field of the plurality of time-sequenced fields in the buffer control command based on the determination result.

公开(公告)号：US20200333984A1

公开(公告)日：2020-10-22

申请号：US16847623

申请日：2020-04-13

Applicant: MONTAGE TECHNOLOGY CO., LTD.

Inventor： Yi LI ,  Gang SHAN ,  Howard Chonghe YANG

IPC: G06F3/06 ,  G06F21/60 ,  G11C8/06 ,  G11C8/18

Abstract: An apparatus controls access to a memory module coupled to a host controller via a data bus to exchange data with the host controller. The apparatus has a configurable information memory and comprises: an access control input port via which the apparatus receives a data access command from the host controller; a control unit to identify a data access command including an access address directed to a predetermined storage region of the memory module, and generate an information processing command based at least on the access address directed to the predetermined storage region, such that the control unit can configure the information memory based on the information processing command or provide the information processing command to the memory module; and an access control output port via which the apparatus provides the information processing command to the memory module, such that the memory module outputs corresponding data information to the host controller based on the information processing command.

公开(公告)号：US20190205048A1

公开(公告)日：2019-07-04

申请号：US16239542

申请日：2019-01-04

Applicant: MONTAGE TECHNOLOGY CO., LTD.

Inventor： Gang SHAN ,  Howard Chonghe YANG ,  Yi LI

IPC: G06F3/06

CPC classification number: G06F3/0622 ,  G06F3/0629 ,  G06F3/0659 ,  G06F3/0673

Abstract: A memory controller and a method for accessing a memory module are provided. The memory controller is coupled between the memory module and a host controller to control the access of the host controller to the memory module. The memory controller comprises: a central buffer coupled to the host controller for receiving a data access command from the host controller, and coupled to the memory module for providing a modified data access command to the memory module; wherein the central buffer comprises an access command processing module, for processing the data access command to generate the modified data access command; and a data buffer coupled to the central buffer for receiving the modified data access command from the central buffer, and coupled between the host controller and the memory module for exchanging data between the host controller and the memory module under the control of the modified data access command.