公开(公告)号：US10727861B2

公开(公告)日：2020-07-28

申请号：US16438842

申请日：2019-06-12

Applicant: Maxlinear, Inc.

Inventor： Chandrajit Debnath ,  Abhishek Ghosh ,  Rishi Mathur ,  Anand Mohan Pappu

IPC: H03M3/00 ,  G06F7/58

Abstract: An analog-to-digital convertor circuit converts the output of a loop filter circuit to a digital signal. A random sequence generation circuit generates a random sequence. Adder circuitry adds the random sequence to the digital signal to generate a randomized digital signal. Noise transfer function impulse response detection circuitry processes the randomized digital signal and the random sequence to determine a noise transfer function impulse response. Loop filter configuration circuitry configures the loop filter circuit based on the noise transfer function impulse response. The random sequence generation circuit may comprises a high-pass sigma delta modulator. The noise transfer function impulse response detection circuitry may determine the noise transfer function impulse response, and the loop filter configuration circuitry may configure the loop filter based on the noise transfer function impulse response. The loop filter configuration circuitry may generate loop filter coefficients based on the noise transfer function impulse response.

公开(公告)号：US20190341926A1

公开(公告)日：2019-11-07

申请号：US16400431

申请日：2019-05-01

Applicant: Maxlinear, Inc.

Inventor： Rishi Mathur ,  Chandrajit Debnath ,  Abhishek Ghosh ,  Anand Mohan Pappu

IPC: H03M1/36 ,  H03M1/12

Abstract: An analog-to-digital converter circuit comprises code-shuffling circuitry, a plurality of digital-to-analog converter circuits, a plurality of difference circuits, and a plurality of latch circuits. The code-shuffling circuitry is operable to shuffle a plurality of digital codes among a plurality of its outputs. The plurality of digital-to-analog converter circuits are operable to convert a digital code on the respective one of the outputs to a corresponding one of a plurality of analog reference voltages. The plurality of difference circuits is operable to generate a respective one of a plurality of difference signals corresponding to a difference between an input voltage and a respective one of the plurality of reference voltages. The plurality of latch circuits is operable to latch a respective one of the plurality of difference signals to a corresponding one of a plurality of digital values.

公开(公告)号：US20190379390A1

公开(公告)日：2019-12-12

申请号：US16438842

申请日：2019-06-12

Applicant: Maxlinear, Inc.

Inventor： Chandrajit Debnath ,  Abhishek Ghosh ,  Rishi Mathur ,  Anand Mohan Pappu

IPC: H03M3/00 ,  G06F7/58

Abstract: An analog-to-digital convertor circuit converts the output of a loop filter circuit to a digital signal. A random sequence generation circuit generates a random sequence. Adder circuitry adds the random sequence to the digital signal to generate a randomized digital signal. Noise transfer function impulse response detection circuitry processes the randomized digital signal and the random sequence to determine a noise transfer function impulse response. Loop filter configuration circuitry configures the loop filter circuit based on the noise transfer function impulse response. The random sequence generation circuit may comprises a high-pass sigma delta modulator. The noise transfer function impulse response detection circuitry may determine the noise transfer function impulse response, and the loop filter configuration circuitry may configure the loop filter based on the noise transfer function impulse response. The loop filter configuration circuitry may generate loop filter coefficients based on the noise transfer function impulse response.

公开(公告)号：US20180198419A1

公开(公告)日：2018-07-12

申请号：US15478713

申请日：2017-04-04

Applicant: MaxLinear, Inc.

Inventor： Prasun Kali Bhattacharyya ,  Abhishek Ghosh ,  Prasenjit Bhowmik

IPC: H03F1/32 ,  H04L7/00 ,  G11B20/22 ,  H03M1/06 ,  H04B1/10 ,  H04B1/04

CPC classification number: H03F1/32 ,  G11B20/22 ,  H03F3/19 ,  H03F3/24 ,  H03F2200/451 ,  H03M1/0614 ,  H03M1/0624 ,  H03M1/66 ,  H04B1/0475 ,  H04B1/10 ,  H04L7/0008

Abstract: Systems and methods are provided for clocking scheme to reduce nonlinear distortion. An example system may comprise at least two processing paths, each comprising at least one circuit exhibiting nonlinear behavior. Nonlinearity may be managed during processing of signals, such as by assessing effects of the nonlinear behavior during the processing of signals, and controlling clocking applied via at least one path based on the assessed effects, to reduce the effects of the nonlinear behavior during the processing of signals, eliminating the need for post-processing corrections. The controlling of clocking may comprise adjusting timing of a clock applied in the at least path, such as by introducing a timing-delay adjustment to a clock when the clock is applied to a circuit after the circuit exhibiting nonlinear behavior. A timing-advancement may be applied to signals processed via the at least one path, particularly before the circuit exhibiting nonlinear behavior.

公开(公告)号：US10187017B2

公开(公告)日：2019-01-22

申请号：US15478713

申请日：2017-04-04

Applicant: MaxLinear, Inc.

Inventor： Prasun Kali Bhattacharyya ,  Abhishek Ghosh ,  Prasenjit Bhowmik

IPC: H04B1/04 ,  H03F1/32 ,  H04L7/00 ,  G11B20/22 ,  H03M1/06 ,  H04B1/10 ,  H03M1/66

Abstract: Systems and methods are provided for clocking scheme to reduce nonlinear distortion. An example system may comprise at least two processing paths, each comprising at least one circuit exhibiting nonlinear behavior. Nonlinearity may be managed during processing of signals, such as by assessing effects of the nonlinear behavior during the processing of signals, and controlling clocking applied via at least one path based on the assessed effects, to reduce the effects of the nonlinear behavior during the processing of signals, eliminating the need for post-processing corrections. The controlling of clocking may comprise adjusting timing of a clock applied in the at least path, such as by introducing a timing-delay adjustment to a clock when the clock is applied to a circuit after the circuit exhibiting nonlinear behavior. A timing-advancement may be applied to signals processed via the at least one path, particularly before the circuit exhibiting nonlinear behavior.

公开(公告)号：US20200021250A1

公开(公告)日：2020-01-16

申请号：US16584423

申请日：2019-09-26

Applicant: MaxLinear, Inc.

Inventor： Prasun Kali Bhattacharyya ,  Abhishek Ghosh ,  Prasenjit Bhowmik

IPC: H03F1/32 ,  H04B1/04 ,  H04B1/10 ,  H03M1/06 ,  G11B20/22 ,  H04L7/00

Abstract: Systems and methods are provided for clocking scheme to reduce nonlinear distortion. An example system may include at least two processing paths, each including at least one circuit exhibiting nonlinear behavior. Nonlinearity may be managed during processing of signals, such as by assessing effects of the nonlinear behavior during the processing of signals, and controlling clocking applied via at least one path based on the assessed effects, to reduce the effects of the nonlinear behavior during the processing of signals, eliminating the need for post-processing corrections. The controlling of clocking may include adjusting timing of a clock applied in the at least path, such as by introducing a timing-delay adjustment to a clock when the clock is applied to a circuit after the circuit exhibiting nonlinear behavior. A timing-advancement may be applied to signals processed via the at least one path, particularly before the circuit exhibiting nonlinear behavior.