公开(公告)号：US10319418B2

公开(公告)日：2019-06-11

申请号：US15918395

申请日：2018-03-12

Applicant: MaxLinear, Inc.

Inventor： Jian-Hung Lin

IPC: G11C7/10 ,  H03M13/27 ,  H03M13/00 ,  G11C7/22

Abstract: Systems and methods are provided for enhanced parallel bit-interleaving. The parallel bit-interleaving may include, in each of a plurality of cycles, reading a number of bits from an input bitstream; processing the read bits, with the processing including applying a first adjustment to a first combination of bits that includes the read bits and additional bits, wherein each of the additional bits includes a previously read bit in the input bitstream or a pre-set bit; when one or more conditional criteria are met, applying a second adjustment to a second combination of bits that includes bits corresponding to previously read bits, wherein the conditional criteria include completing processing of a full column; writing into memory a number of bits corresponding to the first combination of bits and/or the second combination of bits; and reading from the memory a number of bits, for generating an output corresponding to the particular cycle.

公开(公告)号：US20170270979A1

公开(公告)日：2017-09-21

申请号：US15459639

申请日：2017-03-15

Applicant: MaxLinear, Inc.

Inventor： Jian-Hung Lin

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1012 ,  G11C7/1006 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/22 ,  H03M13/271 ,  H03M13/6561

Abstract: Systems and methods are provided for parallel column twist interleaving. Parallel bit-interleaving with column twist may be applied to an input bitstream based on one or more interleaving parameters. Bits in the input bitstream may be read, in sets having size based on a first interleaving parameter, and may then be processed based on a second interleaving parameter. The processing may comprise applying a shift to a combination of bits that include a current bit set and additional bits corresponding to previously processed bit sets and/or pre-set bits. The shift may be determined based on a column twist associated with the current corresponding. Bits generated based on processing in current and/or previous cycles may be stored into memory, and bits may be read from the memory, based on a third interleaving parameter, for generating an output interleaved bitstream.

公开(公告)号：US09916878B2

公开(公告)日：2018-03-13

申请号：US15459639

申请日：2017-03-15

Applicant: MaxLinear, Inc.

Inventor： Jian-Hung Lin

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1012 ,  G11C7/1006 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/22 ,  H03M13/271 ,  H03M13/6561

Abstract: Systems and methods are provided for parallel column twist interleaving. Parallel bit-interleaving with column twist may be applied to an input bitstream based on one or more interleaving parameters. Bits in the input bitstream may be read, in sets having size based on a first interleaving parameter, and may then be processed based on a second interleaving parameter. The processing may comprise applying a shift to a combination of bits that include a current bit set and additional bits corresponding to previously processed bit sets and/or pre-set bits. The shift may be determined based on a column twist associated with the current corresponding. Bits generated based on processing in current and/or previous cycles may be stored into memory, and bits may be read from the memory, based on a third interleaving parameter, for generating an output interleaved bitstream.

公开(公告)号：US20180261265A1

公开(公告)日：2018-09-13

申请号：US15918395

申请日：2018-03-12

Applicant: MaxLinear, Inc.

Inventor： Jian-Hung Lin

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1012 ,  G11C7/1006 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/22 ,  H03M13/271 ,  H03M13/6561

Abstract: Systems and methods are provided for enhanced parallel bit-interleaving. The parallel bit-interleaving may include, in each of a plurality of cycles, reading a number of bits from an input bitstream; processing the read bits, with the processing including applying a first adjustment to a first combination of bits that includes the read bits and additional bits, wherein each of the additional bits includes a previously read bit in the input bitstream or a pre-set bit; when one or more conditional criteria are met, applying a second adjustment to a second combination of bits that includes bits corresponding to previously read bits, wherein the conditional criteria include completing processing of a full column; writing into memory a number of bits corresponding to the first combination of bits and/or the second combination of bits; and reading from the memory a number of bits, for generating an output corresponding to the particular cycle