公开(公告)号：US20140301133A1

公开(公告)日：2014-10-09

申请号：US14244327

申请日：2014-04-03

Applicant: MaxLinear, Inc.

Inventor： Kimihiko Imura ,  Jianping Yang

IPC: G11C11/24

CPC classification number: G11C11/24 ,  H01L27/0207 ,  H01L27/10805

Abstract: Methods and systems for a high-density, low-cost, CMOS compatible memory may comprise a memory cell on a chip, the memory cell comprising: a plurality of capacitor/switch pairs, where for each pair comprising a switch and a capacitor, a source terminal of the switch is coupled to a gate terminal of the capacitor. The memory cell may also comprise a reset transistor, a biasing circuit, and a source follower. A drain terminal of each switch may be coupled to a floating node that couples a source terminal of the reset transistor and a gate terminal of the source follower. Drain and source terminals of each of the switches of the plurality of capacitor/switch pairs may be coupled to ground. A number of the plurality of capacitor/switch pairs may indicate a number of bits in the memory. The biasing circuit may comprise a current mirror. A bit-line for the memory cell may be coupled to a source terminal of the source follower. The bit-line may comprise a metal trace.

Abstract translation: 用于高密度，低成本的CMOS兼容存储器的方法和系统可以包括芯片上的存储器单元，所述存储单元包括：多个电容器/开关对，其中对于包括开关和电容器的每一对， 开关的源极端子耦合到电容器的栅极端子。 存储单元还可以包括复位晶体管，偏置电路和源极跟随器。 每个开关的漏极端子可以耦合到浮动节点，该浮动节点耦合复位晶体管的源极端子和源极跟随器的栅极端子。 多个电容器/开关对中的每个开关的漏极和源极端子可以耦合到地。 多个电容器/开关对中的多个可以指示存储器中的位数。 偏置电路可以包括电流镜。 存储器单元的位线可以耦合到源极跟随器的源极端子。 位线可以包括金属迹线。