公开(公告)号：US20250047061A1

公开(公告)日：2025-02-06

申请号：US18791337

申请日：2024-07-31

Applicant: MaxLinear, Inc.

Inventor： Abdelkrim El Amili ,  Mario Milicevic ,  Curtis Ling

IPC: H01S5/026 ,  H01S5/02345

Abstract: A co-packaged photonics device includes a photonics device and a photonics driver. The photonics device has an intrinsic impedance and the photonics device is attached to a substrate. The photonics driver is attached to the substrate and is adjacent to the photonics device. The photonics driver includes one or more electrical connections with the photonics device. The photonics driver is configured to drive the photonics device at the intrinsic impedance.

公开(公告)号：US20250141560A1

公开(公告)日：2025-05-01

申请号：US18929528

申请日：2024-10-28

Applicant: MaxLinear, Inc.

Inventor： Abdelkrim El Amili ,  Mario Milicevic ,  Curtis Ling

IPC: H04B10/50 ,  G02B6/40 ,  H04B10/071 ,  H04B10/40

Abstract: An electro-absorption modulated laser may include a first diode and a second diode. The first diode may be operable to receive a first voltage and generate a first output. The second diode may be coupled to the first diode and may be operable to receive a second voltage. The second diode may generate a photocurrent using the first output and the second voltage.

公开(公告)号：US20190296929A1

公开(公告)日：2019-09-26

申请号：US16356077

申请日：2019-03-18

Applicant: Maxlinear, Inc.

Inventor： Mario Milicevic ,  Ioannis Spyropoulos

IPC: H04L12/28 ,  H04B1/10 ,  H03F1/32 ,  H03F3/24

Abstract: A transmitter is configured to generate a DOCSIS signal for transmission onto a frequency-selective coaxial cable. The transmitter comprises a first reverse tilt filter circuit, a digital predistortion circuit, a forward tilt filter, a wideband equalizer, a second reverse tilt filter, and a power amplifier. The responses of the tilt filters may be set based on the frequency response of the frequency-selective coaxial cable to which the transmitter is intended to be coupled. The predistortion circuit may compensate for distortion introduced by circuitry of the transmitter. The equalizer circuit may be operable to compensate for undesired linear response of other circuitry of the transmitter.

公开(公告)号：US10764078B2

公开(公告)日：2020-09-01

申请号：US16356077

申请日：2019-03-18

Applicant: Maxlinear, Inc.

Inventor： Mario Milicevic ,  Ioannis Spyropoulos

IPC: H04L12/28 ,  H03F3/24 ,  H03F1/32 ,  H04B1/10

Abstract: A transmitter is configured to generate a DOCSIS signal for transmission onto a frequency-selective coaxial cable. The transmitter comprises a first reverse tilt filter circuit, a digital predistortion circuit, a forward tilt filter, a wideband equalizer, a second reverse tilt filter, and a power amplifier. The responses of the tilt filters may be set based on the frequency response of the frequency-selective coaxial cable to which the transmitter is intended to be coupled. The predistortion circuit may compensate for distortion introduced by circuitry of the transmitter. The equalizer circuit may be operable to compensate for undesired linear response of other circuitry of the transmitter.

公开(公告)号：US10374633B2

公开(公告)日：2019-08-06

申请号：US15619764

申请日：2017-06-12

Applicant: Maxlinear, Inc.

Inventor： Mario Milicevic ,  Glenn Gulak

IPC: H03M13/11 ,  H03M13/37 ,  H03M13/00 ,  H03M13/53

Abstract: A Low-Density Parity-Check (LDPC) decoder and a method for LDPC decoding are provided. The LDPC decoder receives a soft-decision input codeword block in which the probability of a bit being a “0” or a “1” is represented as a log-likelihood ratio (LLR). During LDPC decoding, a sequence of hardware logic units iteratively updates the soft-decision input codeword block until a valid codeword is found or a maximum number of decoding iterations is reached. Each hardware logic unit comprises a check node (CN) update logic unit and a variable node (VN) update logic unit. The CN update logic units are coupled via a closed CN path, and the VN update logic units are coupled via a closed VN path. Aspects of this LDPC decoder alleviate the global routing and energy efficiency challenges of traditional LDPC decoders, to enable multi-rate, multi-Gb/s decoding without compromising error correction performance in next-generation systems and future CMOS technology nodes.

公开(公告)号：US20180013446A1

公开(公告)日：2018-01-11

申请号：US15619764

申请日：2017-06-12

Applicant: Maxlinear, Inc.

Inventor： Mario Milicevic ,  Glenn Gulak

IPC: H03M13/11 ,  H03M13/37

CPC classification number: H03M13/1174 ,  H03M13/112 ,  H03M13/1122 ,  H03M13/1128 ,  H03M13/114 ,  H03M13/116 ,  H03M13/3746 ,  H03M13/635 ,  H03M13/6502 ,  H03M13/6505 ,  H03M13/6516

Abstract: A Low-Density Parity-Check (LDPC) decoder and a method for LDPC decoding are provided. The LDPC decoder receives a soft-decision input codeword block in which the probability of a bit being a “0” or a “1” is represented as a log-likelihood ratio (LLR). During LDPC decoding, a sequence of hardware logic units iteratively updates the soft-decision input codeword block until a valid codeword is found or a maximum number of decoding iterations is reached. Each hardware logic unit comprises a check node (CN) update logic unit and a variable node (VN) update logic unit. The CN update logic units are coupled via a closed CN path, and the VN update logic units are coupled via a closed VN path. Aspects of this LDPC decoder alleviate the global routing and energy efficiency challenges of traditional LDPC decoders, to enable multi-rate, multi-Gb/s decoding without compromising error correction performance in next-generation systems and future CMOS technology nodes.