公开(公告)号：US20160224375A1

公开(公告)日：2016-08-04

申请号：US14751887

申请日：2015-06-26

Applicant: MediaTek Inc.

Inventor： Mong-Ling CHIAO ,  Pokun TSENG

IPC: G06F9/48

CPC classification number: G06F9/4843 ,  G06F11/3476 ,  G06F11/348 ,  G06F2201/88 ,  G06F2209/508

Abstract: Computer system including storage unit and processing unit including performance monitoring unit (PMU) for performance monitoring on tasks is provided. Processing unit is configured to provide a callback function at location at which a task switch is being performed, reset a counter for external access counting of PMU when first task switch which is to switch execution of tasks to first task occurs, read counted value from counter and record read value into a log of storage unit as record of first task when second task switch which is to switch execution of tasks from first task to second task occurs, and reset counter for second task after log is generated. Records of first task in log within a predetermined time period are summed to analyze performance of first task within predetermined time period so as to determine performance of external access of first task for specific event.

Abstract translation: 提供包括存储单元和处理单元在内的计算机系统，包括用于性能监视任务的性能监控单元（PMU）。 处理单元被配置为在执行任务切换的位置处提供回调函数，当第一个任务切换执行任务到第一个任务时，复位用于PMU的外部访问计数的计数器，从计数器读取计数值 并将第二任务切换到将第一任务切换到第二任务的第二任务切换时，将读取的值作为第一任务的记录记录在存储单元的日志中，并且生成日志后，对第二任务进行复位计数。 将在预定时间段内的日志中的第一任务的记录相加以分析在预定时间段内的第一任务的性能，以便确定特定事件的第一任务的外部访问的性能。

公开(公告)号：US20160188233A1

公开(公告)日：2016-06-30

申请号：US14632135

申请日：2015-02-26

Applicant: MediaTek Inc.

Inventor： Mong-Ling CHIAO

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0679

Abstract: A controller for interfacing between a host and a flash memory is provided. The flash memory includes a plurality of data blocks and a plurality of spare blocks. The controller includes a memory unit and a computation unit. The computation unit is configured to perform a cleaning procedure of the flash memory, wherein whenever the computation unit has finished copying a valid page of a source block in the plurality of data blocks to a spare page of a destination block in the plurality of spare blocks during the cleaning procedure, the computation unit determines whether a request is coming from the host, if so, the computation unit suspends the cleaning procedure and responds to the request from the host, if not, the computation unit continues the cleaning procedure.

Abstract translation: 提供了用于在主机和闪存之间进行接口的控制器。 闪速存储器包括多个数据块和多个备用块。 控制器包括存储器单元和计算单元。 计算单元被配置为执行闪速存储器的清洁过程，其中每当计算单元完成将多个数据块中的源块的有效页复制到多个备用块中的目的地块的备用页时 在清洁过程中，计算单元确定请求是否来自主机，如果是，则计算单元暂停清除过程并响应来自主机的请求，否则计算单元继续执行清除过程。

公开(公告)号：US20160132442A1

公开(公告)日：2016-05-12

申请号：US14535625

申请日：2014-11-07

Applicant: MediaTek Inc.

Inventor： Mong-Ling CHIAO

IPC: G06F13/28 ,  G06F12/08 ,  G06F13/40

CPC classification number: G06F13/28 ,  G06F12/0893 ,  G06F13/4027 ,  G06F2212/6022 ,  Y02D10/14 ,  Y02D10/151

Abstract: A data writing system is provided. A processing unit includes at least one core processor. The dynamic random access memory (DRAM) includes a user buffer storing data to be written to a storage device, a buffer cache and a direct memory access (DMA) buffer. The processing unit executes a plurality of write transactions for moving a portion of the data from the user buffer of the DRAM to the storage device via a first write path, and the remainder of the data from the user buffer of the DRAM to the storage device via a second write path. The first write path passes through the buffer cache of the DRAM, and the second write path does not pass through the buffer cache of the DRAM.

Abstract translation: 提供数据写入系统。 处理单元包括至少一个核心处理器。 动态随机存取存储器（DRAM）包括存储要写入存储装置的数据的用户缓冲器，缓冲器高速缓冲存储器和直接存储器访问（DMA）缓冲器。 处理单元执行多个写入事务，用于经由第一写入路径将来自DRAM的用户缓冲器的数据的一部分移动到存储设备，并且剩余的数据从DRAM的用户缓冲区移动到存储设备 通过第二写入路径。 第一写路径通过DRAM的缓冲高速缓存，第二写路径不通过DRAM的缓冲高速缓存。